From patchwork Wed Apr 19 08:27:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Liebler X-Patchwork-Id: 752130 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3w7FVW6nZGz9s2x for ; Wed, 19 Apr 2017 18:27:31 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="w4+s4HNp"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:subject:to:references:from:date:mime-version :in-reply-to:content-type:content-transfer-encoding:message-id; q=dns; s=default; b=m7gHCfCDC1yI5zoReVmBe6GpR0mEUWAi1nE228tEZxO EEwGT7T6H5+wFnBZ/46nt4Swc4w7R+B4KUWDFTCO/b2jmW502kOjerQyoiTH4XYp nvdzxO43VCuD/x+TtUjAZzjPtvdUM8yMTkscpFY9x5CcfCTUT32FchGM+FgS1tjg = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:subject:to:references:from:date:mime-version :in-reply-to:content-type:content-transfer-encoding:message-id; s=default; bh=CDcpUSgXvKxB9/8MbBg8VW2/5Pw=; b=w4+s4HNpm0d2mGeKM Mu2OEBVMpE3m/FeIb1iOKtNFiUHaaSJSpsJhJ/k0bZIGSEJZQgVjYAsVRoJyV872 NJHQp69DYo7WEPKaFxiE6KYscQjOLnUkdF/lZiQQUHTEzeiF0qkhy7sI9cNwm1iq rFXlpnMgaURJWRj37pEk/Av0Dw= Received: (qmail 34662 invoked by alias); 19 Apr 2017 08:27:22 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 34643 invoked by uid 89); 19 Apr 2017 08:27:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=9215 X-HELO: mx0a-001b2d01.pphosted.com Subject: Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros. To: libc-alpha@sourceware.org References: <1481905917-15654-1-git-send-email-stli@linux.vnet.ibm.com> <5857CF10.1060100@arm.com> <628f6311-239c-5eea-572c-c2acae6fcbee@linux.vnet.ibm.com> <1487017743.16322.80.camel@redhat.com> <60a34645-17e4-6693-1343-03c55b0c47ad@linux.vnet.ibm.com> <1487437038.20203.68.camel@redhat.com> <25ad863b-6f20-bfb7-95e6-3b04a2b3eee8@linux.vnet.ibm.com> <1487598702.20203.138.camel@redhat.com> <1491487245.5374.161.camel@redhat.com> From: Stefan Liebler Date: Wed, 19 Apr 2017 10:27:16 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: X-TM-AS-GCONF: 00 x-cbid: 17041908-0040-0000-0000-0000038B0D3E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17041908-0041-0000-0000-00001FC0AAE9 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-19_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1704190079 On 04/18/2017 11:17 PM, Joseph Myers wrote: > On Thu, 6 Apr 2017, Torvald Riegel wrote: > >> Have you been actually looking at these? The next line in the file is a >> pretty obvious hint that this is an LLSC machine, and atomic_exchange >> isn't defined anywhere: >> >>> /* Microblaze does not have byte and halfword forms of load and reserve and >>> diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h >>> index 54c182b..3d9da0c 100644 >>> --- a/sysdeps/mips/atomic-machine.h >>> >>> +++ b/sysdeps/mips/atomic-machine.h >>> >>> @@ -50,6 +50,8 @@ typedef uintmax_t uatomic_max_t; >>> #define __HAVE_64B_ATOMICS 1 >>> #endif >>> >>> +#define ATOMIC_EXCHANGE_USES_CAS 0 >>> >>> + >> >> Please ask the MIPS maintainers to review this. > > MIPS is an LLSC machine. However, XLP has a direct atomic exchange > instruction (so that will be used if _MIPS_ARCH_XLP is defined, in the > case where this header is using compiler builtins). > Thanks for review. I've changed the patch to: --- a/sysdeps/mips/atomic-machine.h +++ b/sysdeps/mips/atomic-machine.h @@ -92,7 +92,15 @@ typedef uintmax_t uatomic_max_t; have no assembly alternative available and want to avoid the __sync_* builtins if at all possible. */ -#define USE_ATOMIC_COMPILER_BUILTINS 1 +# define USE_ATOMIC_COMPILER_BUILTINS 1 + +/* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange + instruction which will be used by __atomic_exchange_n. */ +# ifdef _MIPS_ARCH_XLP +# define ATOMIC_EXCHANGE_USES_CAS 0 +# else +# define ATOMIC_EXCHANGE_USES_CAS 1 +# endif /* Compare and exchange. For all "bool" routines, we return FALSE if exchange succesful. */ @@ -213,7 +221,8 @@ typedef uintmax_t uatomic_max_t; /* This implementation using inline assembly will be removed once glibc requires GCC 4.8 or later to build. */ -#define USE_ATOMIC_COMPILER_BUILTINS 0 +# define USE_ATOMIC_COMPILER_BUILTINS 0 +# define ATOMIC_EXCHANGE_USES_CAS 1 /* Compare and exchange. For all of the "xxx" routines, we expect a "__prev" and a "__cmp" variable to be provided by the enclosing scope,