| Message ID | cf9fc950116aefcc4cf1ed310e42aef38d2f8de7.camel@mengyan1223.wang |
|---|---|
| State | New |
| Headers | show |
| Series | mips: increase stack alignment in clone to match the ABI | expand |
diff --git a/sysdeps/unix/sysv/linux/mips/clone.S b/sysdeps/unix/sysv/linux/mips/clone.S index 43a5ad3a40..81d814ba4d 100644 --- a/sysdeps/unix/sysv/linux/mips/clone.S +++ b/sysdeps/unix/sysv/linux/mips/clone.S @@ -57,9 +57,9 @@ NESTED(__clone,4*SZREG,sp) /* Align stack to 4/8 bytes per the ABI. */ #if _MIPS_SIM == _ABIO32 - li t0,-4 -#else li t0,-8 +#else + li t0,-16 #endif and a1,a1,t0
Hi Joseph, Sorry for this, but I have to admit I've made an error in the previous patch. In MIPS documentations one "word" is defined 32-bit (4-byte), so a "doubleword" is 8-byte and a "quadword" is 16-byte. I misinterpreted "doubleword" as a "dword" we normally uses for 4-byte, so the alignment is actually insufficient. I'm not sure why "tst-misaligned-stack" passed with the previous problematic patch on my board. Maybe it was pure luck, or my CPU used to test the patch supports some non-standard unaligned access. The following patch should fix this: In "mips: align stack in clone [BZ #28223]" (commit 1f51cd9a860ee45eee8a56fb2ba925267a2a7bfe) I made a mistake: I misbelieved one "word" was 2-byte and "doubleword" should be 4-byte. But in MIPS ABI one "word" is defined 32-bit (4-byte), so "doubleword" is 8-byte [1], and "quadword" is 16-byte [2]. [1]: "System V Application Binary Interface: MIPS(R) RISC Processor Supplement, 3rd edition", page 3-31 [2]: "MIPSpro(TM) 64-Bit Porting and Transition Guide", page 23 --- sysdeps/unix/sysv/linux/mips/clone.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)