| Message ID | 20241108110200.706-1-julian.oerv@isrc.iscas.ac.cn |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Use builtin for ffs and ffsll while supported extension available | expand |
On Fri, 2024-11-08 at 19:02 +0800, Julian Zhu wrote: > Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb > extension. With special `-march` flags defined, we can generate more > simplified code compared to the generic implementation of > `ffs`/`ffsll`. > > Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn> > --- > sysdeps/riscv/math-use-builtins-ffs.h | 10 ++++++++++ > 1 file changed, 10 insertions(+) > create mode 100644 sysdeps/riscv/math-use-builtins-ffs.h > > diff --git a/sysdeps/riscv/math-use-builtins-ffs.h > b/sysdeps/riscv/math-use-builtins-ffs.h > new file mode 100644 > index 0000000000..7a125f11bc > --- /dev/null > +++ b/sysdeps/riscv/math-use-builtins-ffs.h > @@ -0,0 +1,10 @@ > +#if __GNUC_PREREQ (12, 0) && defined __riscv_zbb > +# define USE_FFS_BUILTIN 1 > +# define USE_FFSLL_BUILTIN 1 > +#elif define __GNUC_PREREQ (13, 0) && defined __riscv_xtheadbb This line is absolutely incorrect, it cannot even pass the preprocessor: $ cpp t.h -o /dev/null t.h:3:5: error: missing binary operator before token "(" 3 | ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min)) | ^ t.h:11:14: note: in expansion of macro '__GNUC_PREREQ' 11 | #elif define __GNUC_PREREQ (13, 0) && defined __riscv_xtheadbb | ^~~~~~~~~~~~~ Have you really tested your patch? > +# define USE_FFS_BUILTIN 0 > +# define USE_FFSLL_BUILTIN 1 > +#else > +# define USE_FFS_BUILTIN 0 > +# define USE_FFSLL_BUILTIN 0 > +#endif
diff --git a/sysdeps/riscv/math-use-builtins-ffs.h b/sysdeps/riscv/math-use-builtins-ffs.h new file mode 100644 index 0000000000..7a125f11bc --- /dev/null +++ b/sysdeps/riscv/math-use-builtins-ffs.h @@ -0,0 +1,10 @@ +#if __GNUC_PREREQ (12, 0) && defined __riscv_zbb +# define USE_FFS_BUILTIN 1 +# define USE_FFSLL_BUILTIN 1 +#elif define __GNUC_PREREQ (13, 0) && defined __riscv_xtheadbb +# define USE_FFS_BUILTIN 0 +# define USE_FFSLL_BUILTIN 1 +#else +# define USE_FFS_BUILTIN 0 +# define USE_FFSLL_BUILTIN 0 +#endif
Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb extension. With special `-march` flags defined, we can generate more simplified code compared to the generic implementation of `ffs`/`ffsll`. Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn> --- sysdeps/riscv/math-use-builtins-ffs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 sysdeps/riscv/math-use-builtins-ffs.h