From patchwork Sat Sep 14 14:26:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Jeanson X-Patchwork-Id: 1985646 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=efficios.com header.i=@efficios.com header.a=rsa-sha256 header.s=smtpout1 header.b=kSHWMxwb; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X5YRQ5t8zz1y2N for ; Sun, 15 Sep 2024 00:27:27 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AE1663858CDB for ; Sat, 14 Sep 2024 14:27:23 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from smtpout.efficios.com (smtpout.efficios.com [IPv6:2607:5300:203:b2ee::31e5]) by sourceware.org (Postfix) with ESMTPS id DDD833858D20 for ; Sat, 14 Sep 2024 14:27:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DDD833858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=efficios.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=efficios.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DDD833858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:5300:203:b2ee::31e5 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726324024; cv=none; b=v0C4+nEihMB75AR0Q359ZY4PuTiWwFEmwYsPJUJLkGrUrTDPskP+DrJ2xUFy1zpickiWa7Beum5IYRSYB5HQIf9MICAs8BdTLeGQ1SteP1xVLbLdEX6pYHYA/jXq1FGvveIcdjUrxaVs/AkvM3uWaQor5n/VPVfmbrbZ8ri5M9o= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726324024; c=relaxed/simple; bh=+sMKenH1EA5JWzGn4x61PVqAsoHxB3Ao7EepH7Anr3c=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=WthmFeyX2ySknibAV10zNjFamd9z5p13m2txMedWBbsjkZnmKZVlEYyD6VLWMQ+3y7b4EDsxYD16ogWdk0Blp7F1xuAB2eYkGlBBsvcwFDScGLlNT6tHr0UDex6kzYqPJeQyP4cnOaqDSKNj++hc2zrjpP3QRrZr0+kjOftmf6Y= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=efficios.com; s=smtpout1; t=1726324020; bh=+sMKenH1EA5JWzGn4x61PVqAsoHxB3Ao7EepH7Anr3c=; h=From:To:Cc:Subject:Date:From; b=kSHWMxwbho0JtAM5d73aO1gHV6O8qNYMVXuAAFMHnpcYSfsUhTTtq+HPt/IgDWoiE ErVUlbW+j2SK5hKtvwJcJXZAUeeXbncAjYmVOeXUv3Cv6eYbDxmv++MHgpKgw+aahz w6bi8ZDMJTfaaI98+orVeuRKkXBQjDEh3dZXK1gbgq+wRkqA0pAjyntLtoLuwrPkyG 83KWQYWTEfB0T3MHGAA5dHFVeniyxcUyJjr96DGA71FWwI4qz40C7hSq5sehIXyqcJ Mt+kVWaZtsxrO39N9uhylVUIFYiIR/X/oc9yMX/Nm0p+hhJ6n5Aon08DMdrAcsI9ID eF1M5Y7eXc+mg== Received: from mj-deb12-aarch64-glibc.internal.efficios.com (96-127-217-162.qc.cable.ebox.net [96.127.217.162]) by smtpout.efficios.com (Postfix) with ESMTPSA id 4X5YQr2KDTz1LHV; Sat, 14 Sep 2024 10:27:00 -0400 (EDT) From: Michael Jeanson To: libc-alpha@sourceware.org Cc: Michael Jeanson , Florian Weimer , Palmer Dabbelt , Darius Rad Subject: [PATCH] nptl: add RSEQ_SIG for RISC-V Date: Sat, 14 Sep 2024 10:26:52 -0400 Message-Id: <20240914142652.8970-1-mjeanson@efficios.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org Enable RSEQ for RISC-V, support was added in Linux 5.18. Signed-off-by: Michael Jeanson --- Cc: Florian Weimer Cc: Palmer Dabbelt Cc: Darius Rad --- sysdeps/unix/sysv/linux/riscv/bits/rseq.h | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/rseq.h diff --git a/sysdeps/unix/sysv/linux/riscv/bits/rseq.h b/sysdeps/unix/sysv/linux/riscv/bits/rseq.h new file mode 100644 index 0000000000..dfc1fc9315 --- /dev/null +++ b/sysdeps/unix/sysv/linux/riscv/bits/rseq.h @@ -0,0 +1,44 @@ +/* Restartable Sequences Linux riscv architecture header. + Copyright (C) 2021-2024 Free Software Foundation, Inc. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +#ifndef _SYS_RSEQ_H +# error "Never use directly; include instead." +#endif + +/* RSEQ_SIG is a signature required before each abort handler code. + + It is a 32-bit value that maps to actual architecture code compiled + into applications and libraries. It needs to be defined for each + architecture. When choosing this value, it needs to be taken into + account that generating invalid instructions may have ill effects on + tools like objdump, and may also have impact on the CPU speculative + execution efficiency in some cases. + + Select the instruction "csrw mhartid, x0" as the RSEQ_SIG. Unlike + other architectures, the ebreak instruction has no immediate field for + distinguishing purposes. Hence, ebreak is not suitable as RSEQ_SIG. + "csrw mhartid, x0" can also satisfy the RSEQ requirement because it + is an uncommon instruction and will raise an illegal instruction + exception when executed in all modes. */ + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define RSEQ_SIG 0xf1401073 +#else +/* RSEQ is currently only supported on Little-Endian. */ +#endif