diff mbox series

nptl: add RSEQ_SIG for RISC-V

Message ID 20240914142652.8970-1-mjeanson@efficios.com
State New
Headers show
Series nptl: add RSEQ_SIG for RISC-V | expand

Commit Message

Michael Jeanson Sept. 14, 2024, 2:26 p.m. UTC 
Enable RSEQ for RISC-V, support was added in Linux 5.18.

Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
---
Cc: Florian Weimer <fweimer@redhat.com>
Cc: Palmer Dabbelt <palmer@rivosinc.com>
Cc: Darius Rad <darius@bluespec.com>
---
 sysdeps/unix/sysv/linux/riscv/bits/rseq.h | 44 +++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/rseq.h
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Patch

diff --git a/sysdeps/unix/sysv/linux/riscv/bits/rseq.h b/sysdeps/unix/sysv/linux/riscv/bits/rseq.h
new file mode 100644
index 0000000000..dfc1fc9315
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/riscv/bits/rseq.h
@@ -0,0 +1,44 @@ 
+/* Restartable Sequences Linux riscv architecture header.
+   Copyright (C) 2021-2024 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <https://www.gnu.org/licenses/>.  */
+
+#include <bits/endian.h>
+
+#ifndef _SYS_RSEQ_H
+# error "Never use <bits/rseq.h> directly; include <sys/rseq.h> instead."
+#endif
+
+/* RSEQ_SIG is a signature required before each abort handler code.
+
+   It is a 32-bit value that maps to actual architecture code compiled
+   into applications and libraries.  It needs to be defined for each
+   architecture.  When choosing this value, it needs to be taken into
+   account that generating invalid instructions may have ill effects on
+   tools like objdump, and may also have impact on the CPU speculative
+   execution efficiency in some cases.
+
+   Select the instruction "csrw mhartid, x0" as the RSEQ_SIG. Unlike
+   other architectures, the ebreak instruction has no immediate field for
+   distinguishing purposes. Hence, ebreak is not suitable as RSEQ_SIG.
+   "csrw mhartid, x0" can also satisfy the RSEQ requirement because it
+   is an uncommon instruction and will raise an illegal instruction
+   exception when executed in all modes.  */
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define RSEQ_SIG	0xf1401073
+#else
+/* RSEQ is currently only supported on Little-Endian.  */
+#endif