| Message ID | 20240707145831.9114-3-jz531210@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/3] RISC-V: Add a macro definition file to check whether the compiler supports extensions. | expand |
diff --git a/sysdeps/riscv/math-use-builtins-ffs.h b/sysdeps/riscv/math-use-builtins-ffs.h new file mode 100644 index 0000000000..8104e29f84 --- /dev/null +++ b/sysdeps/riscv/math-use-builtins-ffs.h @@ -0,0 +1,10 @@ +#if defined COMPILER_ZBB_AVAIL && defined __riscv_zbb +# define USE_FFS_BUILTIN 1 +# define USE_FFSLL_BUILTIN 1 +#elif defined COMPILER_XTHEADBB_AVAIL && defined __riscv_xtheadbb +# define USE_FFS_BUILTIN 0 +# define USE_FFSLL_BUILTIN 1 +#else +# define USE_FFS_BUILTIN 0 +# define USE_FFSLL_BUILTIN 0 +#endif
Hardware ctz/ctzw instructions are available in the RISC-V Zbb extension, and the similar ctz instruction th.ff1 is available in the RISC-V XTheadBb extension. We can get more simplified code compared to the generic implement of ffs/ffsll. Signed-off-by: Julian Zhu <jz531210@gmail.com> --- sysdeps/riscv/math-use-builtins-ffs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 sysdeps/riscv/math-use-builtins-ffs.h