From patchwork Mon May 27 06:55:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Pandey X-Patchwork-Id: 1939677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Vnmcc0DLTz20PT for ; Mon, 27 May 2024 16:55:27 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B8D22385840E for ; Mon, 27 May 2024 06:55:25 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by sourceware.org (Postfix) with ESMTPS id 163173858D28 for ; Mon, 27 May 2024 06:55:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 163173858D28 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 163173858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716792908; cv=none; b=OpzuKvV73nCm6WhlU7g4wVnxfGx8reSDr21mssfYGn6DVUdCEpQrIVnJCBthAQm5iRAMEEOCVWnCaUaaBGJemb8y/ltK7Nehzw8BVpMjAZo070X5a6CCB1n6iooJ9HO4TsNTtg08iyua/lKRajlfgnA22IaX4o1Rp4NH5NoG/kY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716792908; c=relaxed/simple; bh=N/zbU5e0EPpt3yiT+LZVSdsWi585lewjEyDZ38BUcD8=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=GxT0fECcoXb6/pN/bOtMQkI8U6dO/BDFlnRU6ygkUKDJo35U+pNZVcgImro4FTeZfDQ/rPKKUdx1+WbTy/wmci0ndPhKP5ZG5uR4Qz5ERWVIpd6QyRw7MFM3Df1oxKyBOJRCCAcGmhdixpfYy19yhEV8/WVewubMAzMEfSJiWYI= ARC-Authentication-Results: i=1; server2.sourceware.org X-CSE-ConnectionGUID: ImxbB4ctT+GNRqz3Kca4DA== X-CSE-MsgGUID: +j3FG1ZKRfmHAjyTJ9TB3A== X-IronPort-AV: E=McAfee;i="6600,9927,11084"; a="13279609" X-IronPort-AV: E=Sophos;i="6.08,191,1712646000"; d="scan'208";a="13279609" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2024 23:55:03 -0700 X-CSE-ConnectionGUID: Ywkz7cLYRmKm97VjoUIziw== X-CSE-MsgGUID: sZdiS5xRTt+NLSpQ8/8sCA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,191,1712646000"; d="scan'208";a="65881736" Received: from scymds03.sc.intel.com ([10.148.94.166]) by fmviesa001.fm.intel.com with ESMTP; 26 May 2024 23:55:03 -0700 Received: from gskx-1.sc.intel.com (gskx-1.sc.intel.com [172.25.149.211]) by scymds03.sc.intel.com (Postfix) with ESMTP id 9E0A572; Sun, 26 May 2024 23:55:03 -0700 (PDT) From: Sunil K Pandey To: libc-alpha@sourceware.org Cc: hjl.tools@gmail.com Subject: [PATCH] i386: Remove Xeon Phi processor support (BZ 31782) Date: Sun, 26 May 2024 23:55:02 -0700 Message-ID: <20240527065502.1765585-1-skpgkp2@gmail.com> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FORGED_GMAIL_RCVD, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HK_RANDOM_ENVFROM, HK_RANDOM_FROM, KAM_DMARC_NONE, KAM_DMARC_STATUS, NML_ADSP_CUSTOM_MED, SPF_HELO_NONE, SPF_SOFTFAIL, SPOOFED_FREEMAIL, SPOOF_GMAIL_MID, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org Xeon Phi ISA support removed in GCC 15 via following commit as a result GLIBC can't build with GCC 15 (BZ 31782). commit e1a7e2c54d52d0ba374735e285b617af44841ace Author: Haochen Jiang Date: Mon May 20 10:43:44 2024 +0800 i386: Remove Xeon Phi ISA support This patch removes Xeon Phi processor support from glibc. Fixes BZ 31782. --- NEWS | 2 + manual/platform.texi | 15 ------- sysdeps/x86/bits/platform/x86.h | 5 --- sysdeps/x86/cpu-features.c | 59 ++++++------------------- sysdeps/x86/cpu-tunables.c | 2 - sysdeps/x86/include/cpu-features.h | 15 ------- sysdeps/x86/tst-cpu-features-cpuinfo.c | 8 ---- sysdeps/x86/tst-cpu-features-supports.c | 7 --- sysdeps/x86/tst-get-cpu-features.c | 10 ----- 9 files changed, 15 insertions(+), 108 deletions(-) diff --git a/NEWS b/NEWS index 84efa46df3..5968c6ca08 100644 --- a/NEWS +++ b/NEWS @@ -44,6 +44,8 @@ Deprecated and removed features, and other changes affecting compatibility: (except for login_tty) due to locking and session management problems. +* Remove Xeon Phi processor support (BZ 31782). + Changes to build and runtime requirements: [Add changes to build and runtime requirements here] diff --git a/manual/platform.texi b/manual/platform.texi index 478b6fdcdf..693a73ec84 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -249,12 +249,6 @@ Leaf (EAX = 23H). @item @code{AVX_VNNI_INT8} -- The AVX-VNNI-INT8 instruction extensions. -@item -@code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions. - -@item -@code{AVX512_4VNNIW} -- The AVX512_4VNNIW instruction extensions. - @item @code{AVX512_BF16} -- The AVX512_BF16 instruction extensions. @@ -289,18 +283,12 @@ extensions. @item @code{AVX512CD} -- The AVX512CD instruction extensions. -@item -@code{AVX512ER} -- The AVX512ER instruction extensions. - @item @code{AVX512DQ} -- The AVX512DQ instruction extensions. @item @code{AVX512F} -- The AVX512F instruction extensions. -@item -@code{AVX512PF} -- The AVX512PF instruction extensions. - @item @code{AVX512VL} -- The AVX512VL instruction extensions. @@ -545,9 +533,6 @@ extended state management using XSAVE/XRSTOR. @item @code{PREFETCHW} -- PREFETCHW instruction. -@item -@code{PREFETCHWT1} -- PREFETCHWT1 instruction. - @item @code{PREFETCHI} -- PREFETCHIT0/1 instructions. diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h index 8b157d99b3..3c15a42ecc 100644 --- a/sysdeps/x86/bits/platform/x86.h +++ b/sysdeps/x86/bits/platform/x86.h @@ -156,8 +156,6 @@ enum x86_cpu_CLFLUSHOPT = x86_cpu_index_7_ebx + 23, x86_cpu_CLWB = x86_cpu_index_7_ebx + 24, x86_cpu_TRACE = x86_cpu_index_7_ebx + 25, - x86_cpu_AVX512PF = x86_cpu_index_7_ebx + 26, - x86_cpu_AVX512ER = x86_cpu_index_7_ebx + 27, x86_cpu_AVX512CD = x86_cpu_index_7_ebx + 28, x86_cpu_SHA = x86_cpu_index_7_ebx + 29, x86_cpu_AVX512BW = x86_cpu_index_7_ebx + 30, @@ -167,7 +165,6 @@ enum = (CPUID_INDEX_7 * 8 * 4 * sizeof (unsigned int) + cpuid_register_index_ecx * 8 * sizeof (unsigned int)), - x86_cpu_PREFETCHWT1 = x86_cpu_index_7_ecx, x86_cpu_AVX512_VBMI = x86_cpu_index_7_ecx + 1, x86_cpu_UMIP = x86_cpu_index_7_ecx + 2, x86_cpu_PKU = x86_cpu_index_7_ecx + 3, @@ -203,8 +200,6 @@ enum x86_cpu_INDEX_7_EDX_0 = x86_cpu_index_7_edx, x86_cpu_SGX_KEYS = x86_cpu_index_7_edx + 1, - x86_cpu_AVX512_4VNNIW = x86_cpu_index_7_edx + 2, - x86_cpu_AVX512_4FMAPS = x86_cpu_index_7_edx + 3, x86_cpu_FSRM = x86_cpu_index_7_edx + 4, x86_cpu_UINTR = x86_cpu_index_7_edx + 5, x86_cpu_INDEX_7_EDX_6 = x86_cpu_index_7_edx + 6, diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 3d7c2819d7..1ec9c5b6d0 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -116,7 +116,6 @@ update_active (struct cpu_features *cpu_features) CPU_FEATURE_SET_ACTIVE (cpu_features, CLFLUSHOPT); CPU_FEATURE_SET_ACTIVE (cpu_features, CLWB); CPU_FEATURE_SET_ACTIVE (cpu_features, SHA); - CPU_FEATURE_SET_ACTIVE (cpu_features, PREFETCHWT1); CPU_FEATURE_SET_ACTIVE (cpu_features, OSPKE); CPU_FEATURE_SET_ACTIVE (cpu_features, WAITPKG); CPU_FEATURE_SET_ACTIVE (cpu_features, GFNI); @@ -218,20 +217,12 @@ update_active (struct cpu_features *cpu_features) CPU_FEATURE_SET (cpu_features, AVX512F); /* Determine if AVX512CD is usable. */ CPU_FEATURE_SET_ACTIVE (cpu_features, AVX512CD); - /* Determine if AVX512ER is usable. */ - CPU_FEATURE_SET_ACTIVE (cpu_features, AVX512ER); - /* Determine if AVX512PF is usable. */ - CPU_FEATURE_SET_ACTIVE (cpu_features, AVX512PF); /* Determine if AVX512VL is usable. */ CPU_FEATURE_SET_ACTIVE (cpu_features, AVX512VL); /* Determine if AVX512DQ is usable. */ CPU_FEATURE_SET_ACTIVE (cpu_features, AVX512DQ); /* Determine if AVX512BW is usable. */ CPU_FEATURE_SET_ACTIVE (cpu_features, AVX512BW); - /* Determine if AVX512_4FMAPS is usable. */ - CPU_FEATURE_SET_ACTIVE (cpu_features, AVX512_4FMAPS); - /* Determine if AVX512_4VNNIW is usable. */ - CPU_FEATURE_SET_ACTIVE (cpu_features, AVX512_4VNNIW); /* Determine if AVX512_BITALG is usable. */ CPU_FEATURE_SET_ACTIVE (cpu_features, AVX512_BITALG); /* Determine if AVX512_IFMA is usable. */ @@ -940,27 +931,17 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht } } + /* Processors with AVX512 and AVX-VNNI won't lower CPU frequency + when ZMM load and store instructions are used. */ + if (!CPU_FEATURES_CPU_P (cpu_features, AVX_VNNI)) + cpu_features->preferred[index_arch_Prefer_No_AVX512] + |= bit_arch_Prefer_No_AVX512; - /* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER - if AVX512ER is available. Don't use AVX512 to avoid lower CPU - frequency if AVX512ER isn't available. */ - if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER)) + /* Avoid RTM abort triggered by VZEROUPPER inside a + transactionally executing RTM region. */ + if (CPU_FEATURE_USABLE_P (cpu_features, RTM)) cpu_features->preferred[index_arch_Prefer_No_VZEROUPPER] |= bit_arch_Prefer_No_VZEROUPPER; - else - { - /* Processors with AVX512 and AVX-VNNI won't lower CPU frequency - when ZMM load and store instructions are used. */ - if (!CPU_FEATURES_CPU_P (cpu_features, AVX_VNNI)) - cpu_features->preferred[index_arch_Prefer_No_AVX512] - |= bit_arch_Prefer_No_AVX512; - - /* Avoid RTM abort triggered by VZEROUPPER inside a - transactionally executing RTM region. */ - if (CPU_FEATURE_USABLE_P (cpu_features, RTM)) - cpu_features->preferred[index_arch_Prefer_No_VZEROUPPER] - |= bit_arch_Prefer_No_VZEROUPPER; - } /* Avoid avoid short distance REP MOVSB on processor with FSRM. */ if (CPU_FEATURES_CPU_P (cpu_features, FSRM)) @@ -1123,13 +1104,9 @@ no_cpuid: CPU_FEATURE_UNSET (cpu_features, F16C); CPU_FEATURE_UNSET (cpu_features, AVX512F); CPU_FEATURE_UNSET (cpu_features, AVX512CD); - CPU_FEATURE_UNSET (cpu_features, AVX512ER); - CPU_FEATURE_UNSET (cpu_features, AVX512PF); CPU_FEATURE_UNSET (cpu_features, AVX512VL); CPU_FEATURE_UNSET (cpu_features, AVX512DQ); CPU_FEATURE_UNSET (cpu_features, AVX512BW); - CPU_FEATURE_UNSET (cpu_features, AVX512_4FMAPS); - CPU_FEATURE_UNSET (cpu_features, AVX512_4VNNIW); CPU_FEATURE_UNSET (cpu_features, AVX512_BITALG); CPU_FEATURE_UNSET (cpu_features, AVX512_IFMA); CPU_FEATURE_UNSET (cpu_features, AVX512_VBMI); @@ -1152,21 +1129,11 @@ no_cpuid: { const char *platform = NULL; - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512CD)) - { - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512ER)) - { - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512PF)) - platform = "xeon_phi"; - } - else - { - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) - && CPU_FEATURE_USABLE_P (cpu_features, AVX512DQ) - && CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)) - GLRO(dl_hwcap) |= HWCAP_X86_AVX512_1; - } - } + if (CPU_FEATURE_USABLE_P (cpu_features, AVX512CD) + && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) + && CPU_FEATURE_USABLE_P (cpu_features, AVX512DQ) + && CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)) + GLRO(dl_hwcap) |= HWCAP_X86_AVX512_1; if (platform == NULL && CPU_FEATURE_USABLE_P (cpu_features, AVX2) diff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c index 89da7a03da..c92603d8c8 100644 --- a/sysdeps/x86/cpu-tunables.c +++ b/sysdeps/x86/cpu-tunables.c @@ -181,8 +181,6 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp) CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512CD, 8); CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512BW, 8); CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512DQ, 8); - CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512ER, 8); - CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512PF, 8); CHECK_GLIBC_IFUNC_CPU_OFF (n, cpu_features, AVX512VL, 8); } CHECK_GLIBC_IFUNC_PREFERRED_BOTH (n, cpu_features, Slow_BSF, 8); diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index cd7bd27cf3..17957ba36c 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -183,15 +183,12 @@ enum #define bit_cpu_CLFLUSHOPT (1u << 23) #define bit_cpu_CLWB (1u << 24) #define bit_cpu_TRACE (1u << 25) -#define bit_cpu_AVX512PF (1u << 26) -#define bit_cpu_AVX512ER (1u << 27) #define bit_cpu_AVX512CD (1u << 28) #define bit_cpu_SHA (1u << 29) #define bit_cpu_AVX512BW (1u << 30) #define bit_cpu_AVX512VL (1u << 31) /* ECX. */ -#define bit_cpu_PREFETCHWT1 (1u << 0) #define bit_cpu_AVX512_VBMI (1u << 1) #define bit_cpu_UMIP (1u << 2) #define bit_cpu_PKU (1u << 3) @@ -224,8 +221,6 @@ enum /* EDX. */ #define bit_cpu_INDEX_7_EDX_0 (1u << 0) #define bit_cpu_INDEX_7_EDX_1 (1u << 1) -#define bit_cpu_AVX512_4VNNIW (1u << 2) -#define bit_cpu_AVX512_4FMAPS (1u << 3) #define bit_cpu_FSRM (1u << 4) #define bit_cpu_UINTR (1u << 5) #define bit_cpu_INDEX_7_EDX_6 (1u << 6) @@ -439,15 +434,12 @@ enum #define index_cpu_CLFLUSHOPT CPUID_INDEX_7 #define index_cpu_CLWB CPUID_INDEX_7 #define index_cpu_TRACE CPUID_INDEX_7 -#define index_cpu_AVX512PF CPUID_INDEX_7 -#define index_cpu_AVX512ER CPUID_INDEX_7 #define index_cpu_AVX512CD CPUID_INDEX_7 #define index_cpu_SHA CPUID_INDEX_7 #define index_cpu_AVX512BW CPUID_INDEX_7 #define index_cpu_AVX512VL CPUID_INDEX_7 /* ECX. */ -#define index_cpu_PREFETCHWT1 CPUID_INDEX_7 #define index_cpu_AVX512_VBMI CPUID_INDEX_7 #define index_cpu_UMIP CPUID_INDEX_7 #define index_cpu_PKU CPUID_INDEX_7 @@ -478,8 +470,6 @@ enum /* EDX. */ #define index_cpu_INDEX_7_EDX_0 CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_1 CPUID_INDEX_7 -#define index_cpu_AVX512_4VNNIW CPUID_INDEX_7 -#define index_cpu_AVX512_4FMAPS CPUID_INDEX_7 #define index_cpu_FSRM CPUID_INDEX_7 #define index_cpu_UINTR CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_6 CPUID_INDEX_7 @@ -691,15 +681,12 @@ enum #define reg_CLFLUSHOPT ebx #define reg_CLWB ebx #define reg_TRACE ebx -#define reg_AVX512PF ebx -#define reg_AVX512ER ebx #define reg_AVX512CD ebx #define reg_SHA ebx #define reg_AVX512BW ebx #define reg_AVX512VL ebx /* ECX. */ -#define reg_PREFETCHWT1 ecx #define reg_AVX512_VBMI ecx #define reg_UMIP ecx #define reg_PKU ecx @@ -730,8 +717,6 @@ enum /* EDX. */ #define reg_INDEX_7_EDX_0 edx #define reg_INDEX_7_EDX_1 edx -#define reg_AVX512_4VNNIW edx -#define reg_AVX512_4FMAPS edx #define reg_FSRM edx #define reg_UINTR edx #define reg_INDEX_7_EDX_6 edx diff --git a/sysdeps/x86/tst-cpu-features-cpuinfo.c b/sysdeps/x86/tst-cpu-features-cpuinfo.c index 0251fb5460..1ba8b6339f 100644 --- a/sysdeps/x86/tst-cpu-features-cpuinfo.c +++ b/sysdeps/x86/tst-cpu-features-cpuinfo.c @@ -118,8 +118,6 @@ do_test (int argc, char **argv) fails += CHECK_PROC (arch_capabilities, ARCH_CAPABILITIES); fails += CHECK_PROC (avx, AVX); fails += CHECK_PROC (avx2, AVX2); - fails += CHECK_PROC (avx512_4fmaps, AVX512_4FMAPS); - fails += CHECK_PROC (avx512_4vnniw, AVX512_4VNNIW); fails += CHECK_PROC (avx512_bf16, AVX512_BF16); fails += CHECK_PROC (avx512_bitalg, AVX512_BITALG); fails += CHECK_PROC (avx512ifma, AVX512_IFMA); @@ -130,10 +128,8 @@ do_test (int argc, char **argv) fails += CHECK_PROC (avx512_vpopcntdq, AVX512_VPOPCNTDQ); fails += CHECK_PROC (avx512bw, AVX512BW); fails += CHECK_PROC (avx512cd, AVX512CD); - fails += CHECK_PROC (avx512er, AVX512ER); fails += CHECK_PROC (avx512dq, AVX512DQ); fails += CHECK_PROC (avx512f, AVX512F); - fails += CHECK_PROC (avx512pf, AVX512PF); fails += CHECK_PROC (avx512vl, AVX512VL); fails += CHECK_PROC (bmi1, BMI1); fails += CHECK_PROC (bmi2, BMI2); @@ -222,10 +218,6 @@ do_test (int argc, char **argv) fails += CHECK_PROC (pku, PKU); fails += CHECK_PROC (popcnt, POPCNT); fails += CHECK_PROC (3dnowprefetch, PREFETCHW); -#if 0 - /* NB: /proc/cpuinfo doesn't report this feature. */ - fails += CHECK_PROC (prefetchwt1, PREFETCHWT1); -#endif #if 0 /* NB: /proc/cpuinfo doesn't report this feature. */ fails += CHECK_PROC (ptwrite, PTWRITE); diff --git a/sysdeps/x86/tst-cpu-features-supports.c b/sysdeps/x86/tst-cpu-features-supports.c index e270c29db7..99c40e36ae 100644 --- a/sysdeps/x86/tst-cpu-features-supports.c +++ b/sysdeps/x86/tst-cpu-features-supports.c @@ -65,10 +65,6 @@ do_test (int argc, char **argv) #endif fails += CHECK_FEATURE_ACTIVE (avx, AVX); fails += CHECK_FEATURE_ACTIVE (avx2, AVX2); -#if __GNUC_PREREQ (7, 0) - fails += CHECK_FEATURE_ACTIVE (avx5124fmaps, AVX512_4FMAPS); - fails += CHECK_FEATURE_ACTIVE (avx5124vnniw, AVX512_4VNNIW); -#endif #if __GNUC_PREREQ (10, 0) fails += CHECK_FEATURE_ACTIVE (avx512bf16, AVX512_BF16); #endif @@ -92,14 +88,12 @@ do_test (int argc, char **argv) #if __GNUC_PREREQ (6, 0) fails += CHECK_FEATURE_ACTIVE (avx512bw, AVX512BW); fails += CHECK_FEATURE_ACTIVE (avx512cd, AVX512CD); - fails += CHECK_FEATURE_ACTIVE (avx512er, AVX512ER); fails += CHECK_FEATURE_ACTIVE (avx512dq, AVX512DQ); #endif #if __GNUC_PREREQ (5, 0) fails += CHECK_FEATURE_ACTIVE (avx512f, AVX512F); #endif #if __GNUC_PREREQ (6, 0) - fails += CHECK_FEATURE_ACTIVE (avx512pf, AVX512PF); fails += CHECK_FEATURE_ACTIVE (avx512vl, AVX512VL); #endif #if __GNUC_PREREQ (5, 0) @@ -148,7 +142,6 @@ do_test (int argc, char **argv) #endif fails += CHECK_FEATURE_ACTIVE (popcnt, POPCNT); #if __GNUC_PREREQ (11, 0) - fails += CHECK_FEATURE_ACTIVE (prefetchwt1, PREFETCHWT1); fails += CHECK_FEATURE_ACTIVE (ptwrite, PTWRITE); fails += CHECK_FEATURE_ACTIVE (rdpid, RDPID); fails += CHECK_FEATURE_ACTIVE (rdrnd, RDRAND); diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c index 659fcc7c25..ebef222716 100644 --- a/sysdeps/x86/tst-get-cpu-features.c +++ b/sysdeps/x86/tst-get-cpu-features.c @@ -124,13 +124,10 @@ do_test (void) CHECK_CPU_FEATURE_PRESENT (CLFLUSHOPT); CHECK_CPU_FEATURE_PRESENT (CLWB); CHECK_CPU_FEATURE_PRESENT (TRACE); - CHECK_CPU_FEATURE_PRESENT (AVX512PF); - CHECK_CPU_FEATURE_PRESENT (AVX512ER); CHECK_CPU_FEATURE_PRESENT (AVX512CD); CHECK_CPU_FEATURE_PRESENT (SHA); CHECK_CPU_FEATURE_PRESENT (AVX512BW); CHECK_CPU_FEATURE_PRESENT (AVX512VL); - CHECK_CPU_FEATURE_PRESENT (PREFETCHWT1); CHECK_CPU_FEATURE_PRESENT (AVX512_VBMI); CHECK_CPU_FEATURE_PRESENT (UMIP); CHECK_CPU_FEATURE_PRESENT (PKU); @@ -155,8 +152,6 @@ do_test (void) CHECK_CPU_FEATURE_PRESENT (SGX_LC); CHECK_CPU_FEATURE_PRESENT (PKS); CHECK_CPU_FEATURE_PRESENT (SGX_KEYS); - CHECK_CPU_FEATURE_PRESENT (AVX512_4VNNIW); - CHECK_CPU_FEATURE_PRESENT (AVX512_4FMAPS); CHECK_CPU_FEATURE_PRESENT (FSRM); CHECK_CPU_FEATURE_PRESENT (UINTR); CHECK_CPU_FEATURE_PRESENT (AVX512_VP2INTERSECT); @@ -309,13 +304,10 @@ do_test (void) CHECK_CPU_FEATURE_ACTIVE (CLFLUSHOPT); CHECK_CPU_FEATURE_ACTIVE (CLWB); CHECK_CPU_FEATURE_ACTIVE (TRACE); - CHECK_CPU_FEATURE_ACTIVE (AVX512PF); - CHECK_CPU_FEATURE_ACTIVE (AVX512ER); CHECK_CPU_FEATURE_ACTIVE (AVX512CD); CHECK_CPU_FEATURE_ACTIVE (SHA); CHECK_CPU_FEATURE_ACTIVE (AVX512BW); CHECK_CPU_FEATURE_ACTIVE (AVX512VL); - CHECK_CPU_FEATURE_ACTIVE (PREFETCHWT1); CHECK_CPU_FEATURE_ACTIVE (AVX512_VBMI); CHECK_CPU_FEATURE_ACTIVE (UMIP); CHECK_CPU_FEATURE_ACTIVE (PKU); @@ -337,8 +329,6 @@ do_test (void) CHECK_CPU_FEATURE_ACTIVE (ENQCMD); CHECK_CPU_FEATURE_ACTIVE (SGX_LC); CHECK_CPU_FEATURE_ACTIVE (PKS); - CHECK_CPU_FEATURE_ACTIVE (AVX512_4VNNIW); - CHECK_CPU_FEATURE_ACTIVE (AVX512_4FMAPS); CHECK_CPU_FEATURE_ACTIVE (FSRM); CHECK_CPU_FEATURE_ACTIVE (AVX512_VP2INTERSECT); CHECK_CPU_FEATURE_ACTIVE (MD_CLEAR);