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([2804:1b3:a7c2:6e56:fc45:bb45:8b35:9b81]) by smtp.gmail.com with ESMTPSA id z7-20020a170903018700b001eb2fb28eabsm8446995plg.227.2024.05.06.10.08.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 10:08:11 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Paul E Murphy Subject: [PATCH v2] powerpc: Fix __fesetround_inline_nocheck on POWER9+ (BZ 31682) Date: Mon, 6 May 2024 14:07:59 -0300 Message-ID: <20240506170807.1644139-1-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org The e68b1151f7460d5fa88c3a567c13f66052da79a7 commit changed the __fesetround_inline_nocheck implementation to use mffscrni (through __fe_mffscrn) instead of mtfsfi. For generic powerpc ceil/floor/trunc, the function is supposed to disable the floating-point inexact exception enablebbit, however mffscrni does not change any exception enable bits. This patch fixes by reverting the optimization for the __fesetround_inline_nocheck. Checked on powerpc-linux-gnu. Reviewed-by: Peter Bergner --- sysdeps/powerpc/fpu/fenv_libc.h | 16 +++++----------- sysdeps/powerpc/fpu/round_to_integer.h | 6 +++--- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index f9167056a8..84b53d5d3e 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -182,19 +182,13 @@ __fesetround_inline (int round) return 0; } -/* Same as __fesetround_inline, however without runtime check to use DFP - mtfsfi syntax (as relax_fenv_state) or if round value is valid. */ +/* Same as __fesetround_inline, but it also disable the floating-point + exceptions (bits 56:63 - VE, OE, UE, ZE, XE, NI, and RN). It does + not check if ROUND is a valid value. */ static inline void -__fesetround_inline_nocheck (const int round) +__fesetround_inline_disable_except (const int round) { -#ifdef _ARCH_PWR9 - __fe_mffscrn (round); -#else - if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) - __fe_mffscrn (round); - else - asm volatile ("mtfsfi 7,%0" : : "n" (round)); -#endif + asm volatile ("mtfsfi 7,%0" : : "n" (round)); } #define FPSCR_MASK(bit) (1 << (31 - (bit))) diff --git a/sysdeps/powerpc/fpu/round_to_integer.h b/sysdeps/powerpc/fpu/round_to_integer.h index b68833640f..c053719530 100644 --- a/sysdeps/powerpc/fpu/round_to_integer.h +++ b/sysdeps/powerpc/fpu/round_to_integer.h @@ -42,14 +42,14 @@ set_fenv_mode (enum round_mode mode) switch (mode) { case CEIL: - __fesetround_inline_nocheck (FE_UPWARD); + __fesetround_inline_disable_except (FE_UPWARD); break; case FLOOR: - __fesetround_inline_nocheck (FE_DOWNWARD); + __fesetround_inline_disable_except (FE_DOWNWARD); break; case TRUNC: case ROUND: - __fesetround_inline_nocheck (FE_TOWARDZERO); + __fesetround_inline_disable_except (FE_TOWARDZERO); break; case NEARBYINT: /* Disable FE_INEXACT exception */