From patchwork Tue Feb 6 16:27:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Jeanson X-Patchwork-Id: 1895836 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=efficios.com header.i=@efficios.com header.a=rsa-sha256 header.s=smtpout1 header.b=k2MKSlIK; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TTpcF3QsJz23g2 for ; Wed, 7 Feb 2024 03:29:33 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5770C3858001 for ; Tue, 6 Feb 2024 16:29:31 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from smtpout.efficios.com (smtpout.efficios.com [167.114.26.122]) by sourceware.org (Postfix) with ESMTPS id D3B8A385842C for ; Tue, 6 Feb 2024 16:28:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D3B8A385842C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=efficios.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=efficios.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D3B8A385842C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=167.114.26.122 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707236898; cv=none; b=vb4M3PjdVPgkjeQuBttJPRbbqBOSEMm5nP/LbVmBBE+CrzAhSZz2qFpmwQjN6NNhhUSCvLwB2TtPaStkIsdINizVtIFocwvozbjvMfEgayDydBzlkgGIxrsZPMygn56JCvTGprP9ZA1rWD0vRER94Mxk+bf2EX10Tx2UAdArMXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707236898; c=relaxed/simple; bh=gAkk6lNSdEZwKwO+dqu9g6pHwfiOTxdf8/EsiHhPmfo=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=QRGOXImGriYSOfd23LoXJDqyDfGRc2x+FlFaWvN0iro3lbUQ05wy/3leC9FMAbYtB0jRCoAPaJtHX+wQ2K2d+2BXyxaKsmTUgN/Q6MMiOn7dM06Y4qFOkBM7M2O3P2k3CYwVc5N99cY1uKXkpZdmjWgEd8MMjs8x0CgCGvHP2Uo= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=efficios.com; s=smtpout1; t=1707236894; bh=gAkk6lNSdEZwKwO+dqu9g6pHwfiOTxdf8/EsiHhPmfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k2MKSlIKp4/RtdaTON6YNqCf4r6EdRu4TzGwqSWNN8wJrFKLzTY3CFWrFKUu6vuYA GT/+0J2EDwaoScZydiQ9YklC+3Uhn86EK4jOe5MDLFEWOAyPFlpkfPylsjCSjv3HRn xmZEz9Ynt5i6wRdnfyvYz54NGl8LWS6isfByvmYKVQThX6DcOwf+uHYoVdlnr2npaL QHn1RqoQDBHhaEiNtyNAFYGCViAx0FrMLcMBMH4SeC2U4M3wZnfXaAmnKv1NO74YNt n7Umzm6h5wHrWPYAJDXGu0Wtj3M4A2ZsBwz2dcx3TmEZpPU93iP+8aEh/GBoIOibMI BFvT8n9VrsMpw== Received: from laptop-mjeanson.internal.efficios.com (192-222-143-198.qc.cable.ebox.net [192.222.143.198]) by smtpout.efficios.com (Postfix) with ESMTPSA id 4TTpZk1dcMzXSM; Tue, 6 Feb 2024 11:28:14 -0500 (EST) From: Michael Jeanson To: libc-alpha@sourceware.org Cc: Mathieu Desnoyers , Michael Jeanson Subject: [PATCH v8 6/8] x86-64: Add rseq_load32_load32_relaxed Date: Tue, 6 Feb 2024 11:27:59 -0500 Message-Id: <20240206162801.882585-7-mjeanson@efficios.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206162801.882585-1-mjeanson@efficios.com> References: <20240206162801.882585-1-mjeanson@efficios.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org From: Mathieu Desnoyers Implement rseq_load32_load32_relaxed() for the x86-64 architecture. This static inline function implements a rseq critical section to load two 32-bit integer values atomically with respect to preemption and signal delivery. This implementation is imported from the librseq project. Signed-off-by: Mathieu Desnoyers Signed-off-by: Michael Jeanson --- .../unix/sysv/linux/x86_64/rseq-internal.h | 109 ++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 sysdeps/unix/sysv/linux/x86_64/rseq-internal.h diff --git a/sysdeps/unix/sysv/linux/x86_64/rseq-internal.h b/sysdeps/unix/sysv/linux/x86_64/rseq-internal.h new file mode 100644 index 0000000000..fdca1b6439 --- /dev/null +++ b/sysdeps/unix/sysv/linux/x86_64/rseq-internal.h @@ -0,0 +1,109 @@ +/* Restartable Sequences internal API. x86_64 macros. + Copyright (C) 2023 Free Software Foundation, Inc. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, \ + start_ip, post_commit_offset, abort_ip) \ + ".pushsection __rseq_cs, \"aw\"\n\t" \ + ".balign 32\n\t" \ + __rseq_str(label) ":\n\t" \ + ".long " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \ + ".quad " __rseq_str(start_ip) ", " __rseq_str(post_commit_offset) ", " __rseq_str(abort_ip) "\n\t" \ + ".popsection\n\t" \ + ".pushsection __rseq_cs_ptr_array, \"aw\"\n\t" \ + ".quad " __rseq_str(label) "b\n\t" \ + ".popsection\n\t" + +#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \ + __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \ + (post_commit_ip - start_ip), abort_ip) + +/* + * Exit points of a rseq critical section consist of all instructions outside + * of the critical section where a critical section can either branch to or + * reach through the normal course of its execution. The abort IP and the + * post-commit IP are already part of the __rseq_cs section and should not be + * explicitly defined as additional exit points. Knowing all exit points is + * useful to assist debuggers stepping over the critical section. + */ +#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \ + ".pushsection __rseq_exit_point_array, \"aw\"\n\t" \ + ".quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n\t" \ + ".popsection\n\t" + +#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \ + "leaq " __rseq_str(cs_label) "(%%rip), %%rax\n\t" \ + "movq %%rax, " __rseq_str(rseq_cs) "\n\t" \ + __rseq_str(label) ":\n\t" + +#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \ + "cmpl %[" __rseq_str(cpu_id) "], " __rseq_str(current_cpu_id) "\n\t" \ + "jnz " __rseq_str(label) "\n\t" + +#define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label) \ + ".pushsection __rseq_failure, \"ax\"\n\t" \ + /* Disassembler-friendly signature: ud1 (%rip),%edi. */ \ + ".byte 0x0f, 0xb9, 0x3d\n\t" \ + ".long " __rseq_str(RSEQ_SIG) "\n\t" \ + __rseq_str(label) ":\n\t" \ + teardown \ + "jmp %l[" __rseq_str(abort_label) "]\n\t" \ + ".popsection\n\t" + +#define RSEQ_ASM_DEFINE_CMPFAIL(label, teardown, cmpfail_label) \ + ".pushsection __rseq_failure, \"ax\"\n\t" \ + __rseq_str(label) ":\n\t" \ + teardown \ + "jmp %l[" __rseq_str(cmpfail_label) "]\n\t" \ + ".popsection\n\t" + +/* + * Load @src1 (32-bit) into @dst1 and load @src2 (32-bit) into @dst2. + */ +#define RSEQ_HAS_LOAD32_LOAD32_RELAXED 1 +static __always_inline int +rseq_load32_load32_relaxed(uint32_t *dst1, uint32_t *src1, + uint32_t *dst2, uint32_t *src2) +{ + __asm__ __volatile__ goto ( + RSEQ_ASM_DEFINE_TABLE(3, 1f, 2f, 4f) /* start, commit, abort */ + /* Start rseq by storing table entry pointer into rseq_cs. */ + RSEQ_ASM_STORE_RSEQ_CS(1, 3b, %%fs:RSEQ_CS_OFFSET(%[rseq_offset])) + "movl %[src1], %%ebx\n\t" + "movl %[src2], %%ecx\n\t" + "movl %%ebx, %[dst1]\n\t" + /* final store */ + "movl %%ecx, %[dst2]\n\t" + "2:\n\t" + RSEQ_ASM_DEFINE_ABORT(4, "", abort) + : /* gcc asm goto does not allow outputs */ + : [rseq_offset] "r" (__rseq_offset), + /* final store input */ + [dst1] "m" (*dst1), + [dst2] "m" (*dst2), + [src1] "m" (*src1), + [src2] "m" (*src2) + : "memory", "cc", "ebx", "ecx", "rax" + : abort + ); + rseq_after_asm_goto(); + return 0; +abort: + rseq_after_asm_goto(); + return -1; +}