diff mbox series

[v2,6/7] linux: Sync Linux 6.6 elf.h

Message ID 20231031163239.4020952-7-adhemerval.zanella@linaro.org
State New
Headers show
Series Updates from Linux 6.6 | expand

Commit Message

Adhemerval Zanella Netto Oct. 31, 2023, 4:32 p.m. UTC
It adds NT_X86_SHST (2fab02b25ae7cf5), NT_RISCV_CSR/NT_RISCV_VECTOR
(9300f00439743c4), and NT_LOONGARCH_HW_BREAK/NT_LOONGARCH_HW_WATCH
(1a69f7a161a78ae).
---
 elf/elf.h | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Joseph Myers Nov. 2, 2023, 9:09 p.m. UTC | #1
On Tue, 31 Oct 2023, Adhemerval Zanella wrote:

> It adds NT_X86_SHST (2fab02b25ae7cf5), NT_RISCV_CSR/NT_RISCV_VECTOR
> (9300f00439743c4), and NT_LOONGARCH_HW_BREAK/NT_LOONGARCH_HW_WATCH
> (1a69f7a161a78ae).

That should be NT_X86_SHSTK, in both the commit message and the patch 
itself.  OK with that fix.
diff mbox series

Patch

diff --git a/elf/elf.h b/elf/elf.h
index 73a64baa79..daac2f79f4 100644
--- a/elf/elf.h
+++ b/elf/elf.h
@@ -796,6 +796,7 @@  typedef struct
 #define NT_386_TLS	0x200		/* i386 TLS slots (struct user_desc) */
 #define NT_386_IOPERM	0x201		/* x86 io permission bitmap (1=deny) */
 #define NT_X86_XSTATE	0x202		/* x86 extended state using xsave */
+#define NT_X86_SHST	0x204		/* x86 SHSTK state */
 #define NT_S390_HIGH_GPRS	0x300	/* s390 upper register halves */
 #define NT_S390_TIMER	0x301		/* s390 timer register */
 #define NT_S390_TODCMP	0x302		/* s390 TOD clock comparator register */
@@ -834,6 +835,8 @@  typedef struct
 #define NT_MIPS_DSP	0x800		/* MIPS DSP ASE registers.  */
 #define NT_MIPS_FP_MODE	0x801		/* MIPS floating-point mode.  */
 #define NT_MIPS_MSA	0x802		/* MIPS SIMD registers.  */
+#define NT_RISCV_CSR	0x900		/* RISC-V Control and Status Registers */
+#define NT_RISCV_VECTOR	0x901		/* RISC-V vector registers */
 #define NT_LOONGARCH_CPUCFG	0xa00	/* LoongArch CPU config registers.  */
 #define NT_LOONGARCH_CSR	0xa01	/* LoongArch control and
 					   status registers.  */
@@ -843,6 +846,8 @@  typedef struct
 					   SIMD Extension registers.  */
 #define NT_LOONGARCH_LBT	0xa04	/* LoongArch Loongson Binary
 					   Translation registers.  */
+#define NT_LOONGARCH_HW_BREAK	0xa05   /* LoongArch hardware breakpoint registers */
+#define NT_LOONGARCH_HW_WATCH	0xa06   /* LoongArch hardware watchpoint registers */
 
 /* Legal values for the note segment descriptor types for object files.  */