Message ID | 20230211174916.1455-1-shiqi@isrc.iscas.ac.cn |
---|---|
State | New |
Headers | show |
Series | riscv: Add macros for FPUCW in fpu_control.h | expand |
On Feb 12 2023, Shiqi Zhang wrote: > +# define _FPU_RM_DYN (7 << 5) That is only valid in an insn encoding, not in the fcsr register. > +/* FPU accrued exception flags */ > +# define _FPU_EXCEPT_NV (1 << 0) > +# define _FPU_EXCEPT_NZ (1 << 1) > +# define _FPU_EXCEPT_OF (1 << 2) > +# define _FPU_EXCEPT_UF (1 << 3) > +# define _FPU_EXCEPT_NX (1 << 4) You got them backwards.
>> +# define _FPU_RM_DYN (7 << 5) > That is only valid in an insn encoding, not in the fcsr register. Thank you very much for the tip! >> +/* FPU accrued exception flags */ >> +# define _FPU_EXCEPT_NV (1 << 0) >> +# define _FPU_EXCEPT_NZ (1 << 1) >> +# define _FPU_EXCEPT_OF (1 << 2) >> +# define _FPU_EXCEPT_UF (1 << 3) >> +# define _FPU_EXCEPT_NX (1 << 4) > You got them backwards. Sorry for my carelessness. I mistakenly assumed that flags in table 11.2 was listed from lower to higher bits. Will send a v2 soon.
diff --git a/sysdeps/riscv/fpu_control.h b/sysdeps/riscv/fpu_control.h index c33798c6bb..5c883be4fe 100644 --- a/sysdeps/riscv/fpu_control.h +++ b/sysdeps/riscv/fpu_control.h @@ -36,6 +36,21 @@ extern fpu_control_t __fpu_control; # define _FPU_DEFAULT 0 # define _FPU_IEEE _FPU_DEFAULT +/* FPU rounding modes */ +# define _FPU_RM_RNE (0 << 5) +# define _FPU_RM_RTZ (1 << 5) +# define _FPU_RM_RDN (2 << 5) +# define _FPU_RM_RUP (3 << 5) +# define _FPU_RM_RMM (4 << 5) +# define _FPU_RM_DYN (7 << 5) + +/* FPU accrued exception flags */ +# define _FPU_EXCEPT_NV (1 << 0) +# define _FPU_EXCEPT_NZ (1 << 1) +# define _FPU_EXCEPT_OF (1 << 2) +# define _FPU_EXCEPT_UF (1 << 3) +# define _FPU_EXCEPT_NX (1 << 4) + /* Type of the control word. */ typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));