| Message ID | 20221018024901.3381469-4-goldstein.w.n@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1,1/7] x86: Optimize memchr-evex.S and implement with VMM headers | expand |
On Mon, Oct 17, 2022 at 7:49 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote: > > Optimizations are: > 1. Use the fact that lzcnt(0) -> VEC_SIZE for memchr to save a branch > in short string case. > 2. Save several instructions in len = [VEC_SIZE, 4 * VEC_SIZE] case. > 3. Use more code-size efficient instructions. > - tzcnt ... -> bsf ... > - vpcmpb $0 ... -> vpcmpeq ... > > Code Size Changes: > memrchr-evex.S : -29 bytes > > Net perf changes: > > Reported as geometric mean of all improvements / regressions from N=10 > runs of the benchtests. Value as New Time / Old Time so < 1.0 is > improvement and 1.0 is regression. > > memrchr-evex.S : 0.949 (Mostly from improvements in small strings) > > Full results attached in email. > > Full check passes on x86-64. > --- > sysdeps/x86_64/multiarch/memrchr-evex.S | 538 ++++++++++++++---------- > 1 file changed, 324 insertions(+), 214 deletions(-) > > diff --git a/sysdeps/x86_64/multiarch/memrchr-evex.S b/sysdeps/x86_64/multiarch/memrchr-evex.S > index 550b328c5a..dbcf52808f 100644 > --- a/sysdeps/x86_64/multiarch/memrchr-evex.S > +++ b/sysdeps/x86_64/multiarch/memrchr-evex.S > @@ -21,17 +21,19 @@ > #if ISA_SHOULD_BUILD (4) > > # include <sysdep.h> > -# include "x86-evex256-vecs.h" > -# if VEC_SIZE != 32 > -# error "VEC_SIZE != 32 unimplemented" > + > +# ifndef VEC_SIZE > +# include "x86-evex256-vecs.h" > # endif > > +# include "reg-macros.h" > + > # ifndef MEMRCHR > -# define MEMRCHR __memrchr_evex > +# define MEMRCHR __memrchr_evex > # endif > > -# define PAGE_SIZE 4096 > -# define VMMMATCH VMM(0) > +# define PAGE_SIZE 4096 > +# define VMATCH VMM(0) > > .section SECTION(.text), "ax", @progbits > ENTRY_P2ALIGN(MEMRCHR, 6) > @@ -43,294 +45,402 @@ ENTRY_P2ALIGN(MEMRCHR, 6) > # endif > jz L(zero_0) > > - /* Get end pointer. Minus one for two reasons. 1) It is necessary for a > - correct page cross check and 2) it correctly sets up end ptr to be > - subtract by lzcnt aligned. */ > + /* Get end pointer. Minus one for three reasons. 1) It is > + necessary for a correct page cross check and 2) it correctly > + sets up end ptr to be subtract by lzcnt aligned. 3) it is a > + necessary step in aligning ptr. */ > leaq -1(%rdi, %rdx), %rax > - vpbroadcastb %esi, %VMMMATCH > + vpbroadcastb %esi, %VMATCH > > /* Check if we can load 1x VEC without cross a page. */ > testl $(PAGE_SIZE - VEC_SIZE), %eax > jz L(page_cross) > > - /* Don't use rax for pointer here because EVEX has better encoding with > - offset % VEC_SIZE == 0. */ > - vpcmpb $0, -(VEC_SIZE)(%rdi, %rdx), %VMMMATCH, %k0 > - kmovd %k0, %ecx > - > - /* Fall through for rdx (len) <= VEC_SIZE (expect small sizes). */ > - cmpq $VEC_SIZE, %rdx > - ja L(more_1x_vec) > -L(ret_vec_x0_test): > - > - /* If ecx is zero (no matches) lzcnt will set it 32 (VEC_SIZE) which > - will guarantee edx (len) is less than it. */ > - lzcntl %ecx, %ecx > - cmpl %ecx, %edx > - jle L(zero_0) > - subq %rcx, %rax > + /* Don't use rax for pointer here because EVEX has better > + encoding with offset % VEC_SIZE == 0. */ > + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rdx), %VMATCH, %k0 > + KMOV %k0, %VRCX > + > + /* If rcx is zero then lzcnt -> VEC_SIZE. NB: there is a > + already a dependency between rcx and rsi so no worries about > + false-dep here. */ > + lzcnt %VRCX, %VRSI > + /* If rdx <= rsi then either 1) rcx was non-zero (there was a > + match) but it was out of bounds or 2) rcx was zero and rdx > + was <= VEC_SIZE so we are done scanning. */ > + cmpq %rsi, %rdx > + /* NB: Use branch to return zero/non-zero. Common usage will > + branch on result of function (if return is null/non-null). > + This branch can be used to predict the ensuing one so there > + is no reason to extend the data-dependency with cmovcc. */ > + jbe L(zero_0) > + > + /* If rcx is zero then len must be > RDX, otherwise since we > + already tested len vs lzcnt(rcx) (in rsi) we are good to > + return this match. */ > + test %VRCX, %VRCX > + jz L(more_1x_vec) > + subq %rsi, %rax > ret > > - /* Fits in aligning bytes of first cache line. */ > + /* Fits in aligning bytes of first cache line for VEC_SIZE == > + 32. */ > +# if VEC_SIZE == 32 > + .p2align 4,, 2 > L(zero_0): > xorl %eax, %eax > ret > - > - .p2align 4,, 9 > -L(ret_vec_x0_dec): > - decq %rax > -L(ret_vec_x0): > - lzcntl %ecx, %ecx > - subq %rcx, %rax > - ret > +# endif > > .p2align 4,, 10 > L(more_1x_vec): > - testl %ecx, %ecx > - jnz L(ret_vec_x0) > - > /* Align rax (pointer to string). */ > andq $-VEC_SIZE, %rax > - > +L(page_cross_continue): > /* Recompute length after aligning. */ > - movq %rax, %rdx > + subq %rdi, %rax > > - /* Need no matter what. */ > - vpcmpb $0, -(VEC_SIZE)(%rax), %VMMMATCH, %k0 > - kmovd %k0, %ecx > - > - subq %rdi, %rdx > - > - cmpq $(VEC_SIZE * 2), %rdx > + cmpq $(VEC_SIZE * 2), %rax > ja L(more_2x_vec) > + > L(last_2x_vec): > + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rax), %VMATCH, %k0 > + KMOV %k0, %VRCX > > - /* Must dec rax because L(ret_vec_x0_test) expects it. */ > - decq %rax > - cmpl $VEC_SIZE, %edx > - jbe L(ret_vec_x0_test) > + test %VRCX, %VRCX > + jnz L(ret_vec_x0_test) > > - testl %ecx, %ecx > - jnz L(ret_vec_x0) > + /* If VEC_SIZE == 64 need to subtract because lzcntq won't > + implicitly add VEC_SIZE to match position. */ > +# if VEC_SIZE == 64 > + subl $VEC_SIZE, %eax > +# else > + cmpb $VEC_SIZE, %al > +# endif > + jle L(zero_2) > > - /* Don't use rax for pointer here because EVEX has better encoding with > - offset % VEC_SIZE == 0. */ > - vpcmpb $0, -(VEC_SIZE * 2)(%rdi, %rdx), %VMMMATCH, %k0 > - kmovd %k0, %ecx > - /* NB: 64-bit lzcnt. This will naturally add 32 to position. */ > + /* We adjusted rax (length) for VEC_SIZE == 64 so need seperate > + offsets. */ > +# if VEC_SIZE == 64 > + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rax), %VMATCH, %k0 > +# else > + vpcmpeqb (VEC_SIZE * -2)(%rdi, %rax), %VMATCH, %k0 > +# endif > + KMOV %k0, %VRCX > + /* NB: 64-bit lzcnt. This will naturally add 32 to position for > + VEC_SIZE == 32. */ > lzcntq %rcx, %rcx > - cmpl %ecx, %edx > - jle L(zero_0) > - subq %rcx, %rax > - ret > - > - /* Inexpensive place to put this regarding code size / target alignments > - / ICache NLP. Necessary for 2-byte encoding of jump to page cross > - case which in turn is necessary for hot path (len <= VEC_SIZE) to fit > - in first cache line. */ > -L(page_cross): > - movq %rax, %rsi > - andq $-VEC_SIZE, %rsi > - vpcmpb $0, (%rsi), %VMMMATCH, %k0 > - kmovd %k0, %r8d > - /* Shift out negative alignment (because we are starting from endptr and > - working backwards). */ > - movl %eax, %ecx > - /* notl because eax already has endptr - 1. (-x = ~(x - 1)). */ > - notl %ecx > - shlxl %ecx, %r8d, %ecx > - cmpq %rdi, %rsi > - ja L(more_1x_vec) > - lzcntl %ecx, %ecx > - cmpl %ecx, %edx > - jle L(zero_1) > - subq %rcx, %rax > + subl %ecx, %eax > + ja L(first_vec_x1_ret) > + /* If VEC_SIZE == 64 put L(zero_0) here as we can't fit in the > + first cache line (this is the second cache line). */ > +# if VEC_SIZE == 64 > +L(zero_0): > +# endif > +L(zero_2): > + xorl %eax, %eax > ret > > - /* Continue creating zero labels that fit in aligning bytes and get > - 2-byte encoding / are in the same cache line as condition. */ > -L(zero_1): > - xorl %eax, %eax > + /* NB: Fits in aligning bytes before next cache line for > + VEC_SIZE == 32. For VEC_SIZE == 64 this is attached to > + L(first_vec_x0_test). */ > +# if VEC_SIZE == 32 > +L(first_vec_x1_ret): > + leaq -1(%rdi, %rax), %rax > ret > +# endif > > - .p2align 4,, 8 > -L(ret_vec_x1): > - /* This will naturally add 32 to position. */ > - bsrl %ecx, %ecx > - leaq -(VEC_SIZE * 2)(%rcx, %rax), %rax > + .p2align 4,, 6 > +L(ret_vec_x0_test): > + lzcnt %VRCX, %VRCX > + subl %ecx, %eax > + jle L(zero_2) > +# if VEC_SIZE == 64 > + /* Reuse code at the end of L(ret_vec_x0_test) as we can't fit > + L(first_vec_x1_ret) in the same cache line as its jmp base > + so we might as well save code size. */ > +L(first_vec_x1_ret): > +# endif > + leaq -1(%rdi, %rax), %rax > ret > > - .p2align 4,, 8 > + .p2align 4,, 6 > +L(loop_last_4x_vec): > + /* Compute remaining length. */ > + subl %edi, %eax > +L(last_4x_vec): > + cmpl $(VEC_SIZE * 2), %eax > + jle L(last_2x_vec) > +# if VEC_SIZE == 32 > + /* Only align for VEC_SIZE == 32. For VEC_SIZE == 64 we need > + the spare bytes to align the loop properly. */ > + .p2align 4,, 10 > +# endif > L(more_2x_vec): > - testl %ecx, %ecx > - jnz L(ret_vec_x0_dec) > > - vpcmpb $0, -(VEC_SIZE * 2)(%rax), %VMMMATCH, %k0 > - kmovd %k0, %ecx > - testl %ecx, %ecx > - jnz L(ret_vec_x1) > + /* Length > VEC_SIZE * 2 so check the first 2x VEC for match and > + return if either hit. */ > + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rax), %VMATCH, %k0 > + KMOV %k0, %VRCX > + > + test %VRCX, %VRCX > + jnz L(first_vec_x0) > + > + vpcmpeqb (VEC_SIZE * -2)(%rdi, %rax), %VMATCH, %k0 > + KMOV %k0, %VRCX > + test %VRCX, %VRCX > + jnz L(first_vec_x1) > > /* Need no matter what. */ > - vpcmpb $0, -(VEC_SIZE * 3)(%rax), %VMMMATCH, %k0 > - kmovd %k0, %ecx > + vpcmpeqb (VEC_SIZE * -3)(%rdi, %rax), %VMATCH, %k0 > + KMOV %k0, %VRCX > > - subq $(VEC_SIZE * 4), %rdx > + /* Check if we are near the end. */ > + subq $(VEC_SIZE * 4), %rax > ja L(more_4x_vec) > > - cmpl $(VEC_SIZE * -1), %edx > - jle L(ret_vec_x2_test) > -L(last_vec): > - testl %ecx, %ecx > - jnz L(ret_vec_x2) > + test %VRCX, %VRCX > + jnz L(first_vec_x2_test) > > + /* Adjust length for final check and check if we are at the end. > + */ > + addl $(VEC_SIZE * 1), %eax > + jle L(zero_1) > > - /* Need no matter what. */ > - vpcmpb $0, -(VEC_SIZE * 4)(%rax), %VMMMATCH, %k0 > - kmovd %k0, %ecx > - lzcntl %ecx, %ecx > - subq $(VEC_SIZE * 3 + 1), %rax > - subq %rcx, %rax > - cmpq %rax, %rdi > - ja L(zero_1) > + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rax), %VMATCH, %k0 > + KMOV %k0, %VRCX > + > + lzcnt %VRCX, %VRCX > + subl %ecx, %eax > + ja L(first_vec_x3_ret) > +L(zero_1): > + xorl %eax, %eax > + ret > +L(first_vec_x3_ret): > + leaq -1(%rdi, %rax), %rax > ret > > - .p2align 4,, 8 > -L(ret_vec_x2_test): > - lzcntl %ecx, %ecx > - subq $(VEC_SIZE * 2 + 1), %rax > - subq %rcx, %rax > - cmpq %rax, %rdi > - ja L(zero_1) > + .p2align 4,, 6 > +L(first_vec_x2_test): > + /* Must adjust length before check. */ > + subl $-(VEC_SIZE * 2 - 1), %eax > + lzcnt %VRCX, %VRCX > + subl %ecx, %eax > + jl L(zero_4) > + addq %rdi, %rax > ret > > - .p2align 4,, 8 > -L(ret_vec_x2): > - bsrl %ecx, %ecx > - leaq -(VEC_SIZE * 3)(%rcx, %rax), %rax > + > + .p2align 4,, 10 > +L(first_vec_x0): > + bsr %VRCX, %VRCX > + leaq (VEC_SIZE * -1)(%rdi, %rax), %rax > + addq %rcx, %rax > ret > > - .p2align 4,, 8 > -L(ret_vec_x3): > - bsrl %ecx, %ecx > - leaq -(VEC_SIZE * 4)(%rcx, %rax), %rax > + /* Fits unobtrusively here. */ > +L(zero_4): > + xorl %eax, %eax > + ret > + > + .p2align 4,, 10 > +L(first_vec_x1): > + bsr %VRCX, %VRCX > + leaq (VEC_SIZE * -2)(%rdi, %rax), %rax > + addq %rcx, %rax > ret > > .p2align 4,, 8 > +L(first_vec_x3): > + bsr %VRCX, %VRCX > + addq %rdi, %rax > + addq %rcx, %rax > + ret > + > + .p2align 4,, 6 > +L(first_vec_x2): > + bsr %VRCX, %VRCX > + leaq (VEC_SIZE * 1)(%rdi, %rax), %rax > + addq %rcx, %rax > + ret > + > + .p2align 4,, 2 > L(more_4x_vec): > - testl %ecx, %ecx > - jnz L(ret_vec_x2) > + test %VRCX, %VRCX > + jnz L(first_vec_x2) > > - vpcmpb $0, -(VEC_SIZE * 4)(%rax), %VMMMATCH, %k0 > - kmovd %k0, %ecx > + vpcmpeqb (%rdi, %rax), %VMATCH, %k0 > + KMOV %k0, %VRCX > > - testl %ecx, %ecx > - jnz L(ret_vec_x3) > + test %VRCX, %VRCX > + jnz L(first_vec_x3) > > /* Check if near end before re-aligning (otherwise might do an > unnecessary loop iteration). */ > - addq $-(VEC_SIZE * 4), %rax > - cmpq $(VEC_SIZE * 4), %rdx > + cmpq $(VEC_SIZE * 4), %rax > jbe L(last_4x_vec) > > - decq %rax > - andq $-(VEC_SIZE * 4), %rax > - movq %rdi, %rdx > - /* Get endptr for loop in rdx. NB: Can't just do while rax > rdi because > - lengths that overflow can be valid and break the comparison. */ > - andq $-(VEC_SIZE * 4), %rdx > + > + /* NB: We setup the loop to NOT use index-address-mode for the > + buffer. This costs some instructions & code size but avoids > + stalls due to unlaminated micro-fused instructions (as used > + in the loop) from being forced to issue in the same group > + (essentially narrowing the backend width). */ > + > + /* Get endptr for loop in rdx. NB: Can't just do while rax > rdi > + because lengths that overflow can be valid and break the > + comparison. */ > +# if VEC_SIZE == 64 > + /* Use rdx as intermediate to compute rax, this gets us imm8 > + encoding which just allows the L(more_4x_vec) block to fit > + in 1 cache-line. */ > + leaq (VEC_SIZE * 4)(%rdi), %rdx > + leaq (VEC_SIZE * -1)(%rdx, %rax), %rax > + > + /* No evex machine has partial register stalls. This can be > + replaced with: `andq $(VEC_SIZE * -4), %rax/%rdx` if that > + changes. */ > + xorb %al, %al > + xorb %dl, %dl > +# else > + leaq (VEC_SIZE * 3)(%rdi, %rax), %rax > + andq $(VEC_SIZE * -4), %rax > + leaq (VEC_SIZE * 4)(%rdi), %rdx > + andq $(VEC_SIZE * -4), %rdx > +# endif > + > > .p2align 4 > L(loop_4x_vec): > - /* Store 1 were not-equals and 0 where equals in k1 (used to mask later > - on). */ > - vpcmpb $4, (VEC_SIZE * 3)(%rax), %VMMMATCH, %k1 > + /* NB: We could do the same optimization here as we do for > + memchr/rawmemchr by using VEX encoding in the loop for access > + to VEX vpcmpeqb + vpternlogd. Since memrchr is not as hot as > + memchr it may not be worth the extra code size, but if the > + need arises it an easy ~15% perf improvement to the loop. */ > + > + cmpq %rdx, %rax > + je L(loop_last_4x_vec) > + /* Store 1 were not-equals and 0 where equals in k1 (used to > + mask later on). */ > + vpcmpb $4, (VEC_SIZE * -1)(%rax), %VMATCH, %k1 > > /* VEC(2/3) will have zero-byte where we found a CHAR. */ > - vpxorq (VEC_SIZE * 2)(%rax), %VMMMATCH, %VMM(2) > - vpxorq (VEC_SIZE * 1)(%rax), %VMMMATCH, %VMM(3) > - vpcmpb $0, (VEC_SIZE * 0)(%rax), %VMMMATCH, %k4 > + vpxorq (VEC_SIZE * -2)(%rax), %VMATCH, %VMM(2) > + vpxorq (VEC_SIZE * -3)(%rax), %VMATCH, %VMM(3) > + vpcmpeqb (VEC_SIZE * -4)(%rax), %VMATCH, %k4 > > - /* Combine VEC(2/3) with min and maskz with k1 (k1 has zero bit where > - CHAR is found and VEC(2/3) have zero-byte where CHAR is found. */ > + /* Combine VEC(2/3) with min and maskz with k1 (k1 has zero bit > + where CHAR is found and VEC(2/3) have zero-byte where CHAR > + is found. */ > vpminub %VMM(2), %VMM(3), %VMM(3){%k1}{z} > vptestnmb %VMM(3), %VMM(3), %k2 > > - /* Any 1s and we found CHAR. */ > - kortestd %k2, %k4 > - jnz L(loop_end) > - > addq $-(VEC_SIZE * 4), %rax > - cmpq %rdx, %rax > - jne L(loop_4x_vec) > > - /* Need to re-adjust rdx / rax for L(last_4x_vec). */ > - subq $-(VEC_SIZE * 4), %rdx > - movq %rdx, %rax > - subl %edi, %edx > -L(last_4x_vec): > + /* Any 1s and we found CHAR. */ > + KORTEST %k2, %k4 > + jz L(loop_4x_vec) > + > > - /* Used no matter what. */ > - vpcmpb $0, (VEC_SIZE * -1)(%rax), %VMMMATCH, %k0 > - kmovd %k0, %ecx > + /* K1 has non-matches for first VEC. inc; jz will overflow rcx > + iff all bytes where non-matches. */ > + KMOV %k1, %VRCX > + inc %VRCX > + jnz L(first_vec_x0_end) > > - cmpl $(VEC_SIZE * 2), %edx > - jbe L(last_2x_vec) > + vptestnmb %VMM(2), %VMM(2), %k0 > + KMOV %k0, %VRCX > + test %VRCX, %VRCX > + jnz L(first_vec_x1_end) > + KMOV %k2, %VRCX > + > + /* Seperate logic for VEC_SIZE == 64 and VEC_SIZE == 32 for > + returning last 2x VEC. For VEC_SIZE == 64 we test each VEC > + individually, for VEC_SIZE == 32 we combine them in a single > + 64-bit GPR. */ > +# if VEC_SIZE == 64 > + test %VRCX, %VRCX > + jnz L(first_vec_x2_end) > + KMOV %k4, %VRCX > +# else > + /* Combine last 2 VEC matches for VEC_SIZE == 32. If rcx (from > + VEC(3)) is zero (no CHAR in VEC(3)) then it won't affect the > + result in rsi (from VEC(4)). If rcx is non-zero then CHAR in > + VEC(3) and bsrq will use that position. */ > + KMOV %k4, %VRSI > + salq $32, %rcx > + orq %rsi, %rcx > +# endif > + bsrq %rcx, %rcx > + addq %rcx, %rax > + ret > > - testl %ecx, %ecx > - jnz L(ret_vec_x0_dec) > + .p2align 4,, 4 > +L(first_vec_x0_end): > + /* rcx has 1s at non-matches so we need to `not` it. We used > + `inc` to test if zero so use `neg` to complete the `not` so > + the last 1 bit represent a match. NB: (-x + 1 == ~x). */ > + neg %VRCX > + bsr %VRCX, %VRCX > + leaq (VEC_SIZE * 3)(%rcx, %rax), %rax > + ret > > + .p2align 4,, 10 > +L(first_vec_x1_end): > + bsr %VRCX, %VRCX > + leaq (VEC_SIZE * 2)(%rcx, %rax), %rax > + ret > > - vpcmpb $0, (VEC_SIZE * -2)(%rax), %VMMMATCH, %k0 > - kmovd %k0, %ecx > +# if VEC_SIZE == 64 > + /* Since we can't combine the last 2x VEC for VEC_SIZE == 64 > + need return label for it. */ > + .p2align 4,, 4 > +L(first_vec_x2_end): > + bsr %VRCX, %VRCX > + leaq (VEC_SIZE * 1)(%rcx, %rax), %rax > + ret > +# endif > > - testl %ecx, %ecx > - jnz L(ret_vec_x1) > > - /* Used no matter what. */ > - vpcmpb $0, (VEC_SIZE * -3)(%rax), %VMMMATCH, %k0 > - kmovd %k0, %ecx > + .p2align 4,, 4 > +L(page_cross): > + /* only lower bits of eax[log2(VEC_SIZE):0] are set so we can > + use movzbl to get the amount of bytes we are checking here. > + */ > + movzbl %al, %ecx > + andq $-VEC_SIZE, %rax > + vpcmpeqb (%rax), %VMATCH, %k0 > + KMOV %k0, %VRSI > > - cmpl $(VEC_SIZE * 3), %edx > - ja L(last_vec) > + /* eax was comptued as %rdi + %rdx - 1 so need to add back 1 > + here. */ > + leal 1(%rcx), %r8d > > - lzcntl %ecx, %ecx > - subq $(VEC_SIZE * 2 + 1), %rax > - subq %rcx, %rax > - cmpq %rax, %rdi > - jbe L(ret_1) > + /* Invert ecx to get shift count for byte matches out of range. > + */ > + notl %ecx > + shlx %VRCX, %VRSI, %VRSI > + > + /* if r8 < rdx then the entire [buf, buf + len] is handled in > + the page cross case. NB: we can't use the trick here we use > + in the non page-cross case because we aren't checking full > + VEC_SIZE. */ > + cmpq %r8, %rdx > + ja L(page_cross_check) > + lzcnt %VRSI, %VRSI > + subl %esi, %edx > + ja L(page_cross_ret) > xorl %eax, %eax > -L(ret_1): > ret > > - .p2align 4,, 6 > -L(loop_end): > - kmovd %k1, %ecx > - notl %ecx > - testl %ecx, %ecx > - jnz L(ret_vec_x0_end) > +L(page_cross_check): > + test %VRSI, %VRSI > + jz L(page_cross_continue) > > - vptestnmb %VMM(2), %VMM(2), %k0 > - kmovd %k0, %ecx > - testl %ecx, %ecx > - jnz L(ret_vec_x1_end) > - > - kmovd %k2, %ecx > - kmovd %k4, %esi > - /* Combine last 2 VEC matches. If ecx (VEC3) is zero (no CHAR in VEC3) > - then it won't affect the result in esi (VEC4). If ecx is non-zero > - then CHAR in VEC3 and bsrq will use that position. */ > - salq $32, %rcx > - orq %rsi, %rcx > - bsrq %rcx, %rcx > - addq %rcx, %rax > - ret > - .p2align 4,, 4 > -L(ret_vec_x0_end): > - addq $(VEC_SIZE), %rax > -L(ret_vec_x1_end): > - bsrl %ecx, %ecx > - leaq (VEC_SIZE * 2)(%rax, %rcx), %rax > + lzcnt %VRSI, %VRSI > + subl %esi, %edx > +L(page_cross_ret): > + leaq -1(%rdi, %rdx), %rax > ret > - > END(MEMRCHR) > #endif > -- > 2.34.1 > Results For: memrchr align,invert_pos ,len ,pos ,seek_char ,__memrchr_evex ,__memrchr_evex_orig 0 ,0 ,0 ,1 ,0 ,3.418 ,3.438 ,0.994 0 ,0 ,0 ,1 ,23 ,3.422 ,3.401 ,1.006 0 ,0 ,1 ,2 ,0 ,4.189 ,4.163 ,1.006 0 ,0 ,1 ,2 ,23 ,4.154 ,4.346 ,0.956 0 ,0 ,10 ,1 ,23 ,4.217 ,4.475 ,0.942 0 ,0 ,10 ,11 ,0 ,4.195 ,4.46 ,0.941 0 ,0 ,10 ,11 ,23 ,4.205 ,4.536 ,0.927 0 ,0 ,10 ,2 ,0 ,4.186 ,4.507 ,0.929 0 ,0 ,10 ,9 ,0 ,4.194 ,4.481 ,0.936 0 ,0 ,10 ,9 ,23 ,4.153 ,4.426 ,0.938 0 ,0 ,1024 ,1024 ,23 ,23.769 ,23.165 ,1.026 0 ,0 ,1024 ,1056 ,23 ,24.087 ,23.455 ,1.027 0 ,0 ,1024 ,1088 ,23 ,24.147 ,23.502 ,1.027 0 ,0 ,1024 ,1120 ,23 ,25.172 ,23.543 ,1.069 0 ,0 ,1024 ,1152 ,23 ,24.004 ,23.58 ,1.018 0 ,0 ,1024 ,1184 ,23 ,24.429 ,23.461 ,1.041 0 ,0 ,1024 ,1216 ,23 ,23.918 ,23.489 ,1.018 0 ,0 ,1024 ,1248 ,23 ,24.118 ,23.375 ,1.032 0 ,0 ,1024 ,1280 ,23 ,23.877 ,23.557 ,1.014 0 ,0 ,1024 ,1312 ,23 ,23.889 ,23.481 ,1.017 0 ,0 ,1024 ,1344 ,23 ,23.984 ,23.555 ,1.018 0 ,0 ,1024 ,1376 ,23 ,24.068 ,23.516 ,1.023 0 ,0 ,1024 ,1408 ,23 ,23.827 ,23.483 ,1.015 0 ,0 ,1024 ,640 ,23 ,13.643 ,13.138 ,1.038 0 ,0 ,1024 ,672 ,23 ,13.559 ,13.102 ,1.035 0 ,0 ,1024 ,704 ,23 ,12.635 ,12.372 ,1.021 0 ,0 ,1024 ,736 ,23 ,12.095 ,12.017 ,1.007 0 ,0 ,1024 ,768 ,23 ,11.178 ,10.992 ,1.017 0 ,0 ,1024 ,800 ,23 ,11.121 ,11.027 ,1.009 0 ,0 ,1024 ,832 ,23 ,10.295 ,10.158 ,1.013 0 ,0 ,1024 ,864 ,23 ,6.441 ,6.427 ,1.002 0 ,0 ,1024 ,896 ,23 ,5.856 ,5.855 ,1.0 0 ,0 ,1024 ,928 ,23 ,5.196 ,5.254 ,0.989 0 ,0 ,1024 ,960 ,23 ,4.723 ,5.233 ,0.902 0 ,0 ,1024 ,992 ,23 ,3.543 ,4.472 ,0.792 0 ,0 ,1056 ,1024 ,23 ,3.325 ,4.322 ,0.769 0 ,0 ,1088 ,1024 ,23 ,4.646 ,5.054 ,0.919 0 ,0 ,11 ,1 ,23 ,4.205 ,4.538 ,0.927 0 ,0 ,11 ,10 ,0 ,4.186 ,4.5 ,0.93 0 ,0 ,11 ,10 ,23 ,4.195 ,4.461 ,0.94 0 ,0 ,11 ,12 ,0 ,4.192 ,4.58 ,0.915 0 ,0 ,11 ,12 ,23 ,4.19 ,4.51 ,0.929 0 ,0 ,11 ,2 ,0 ,4.187 ,4.506 ,0.929 0 ,0 ,112 ,16 ,23 ,5.98 ,6.449 ,0.927 0 ,0 ,1120 ,1024 ,23 ,5.18 ,5.246 ,0.987 0 ,0 ,1152 ,1024 ,23 ,5.842 ,5.936 ,0.984 0 ,0 ,1184 ,1024 ,23 ,6.452 ,6.508 ,0.992 0 ,0 ,12 ,1 ,23 ,4.195 ,4.605 ,0.911 0 ,0 ,12 ,11 ,0 ,4.184 ,4.469 ,0.936 0 ,0 ,12 ,11 ,23 ,4.173 ,4.454 ,0.937 0 ,0 ,12 ,13 ,0 ,4.184 ,4.527 ,0.924 0 ,0 ,12 ,13 ,23 ,4.199 ,4.48 ,0.937 0 ,0 ,12 ,2 ,0 ,4.174 ,4.475 ,0.933 0 ,0 ,1216 ,1024 ,23 ,11.653 ,13.008 ,0.896 0 ,0 ,1248 ,1024 ,23 ,11.125 ,10.955 ,1.016 0 ,0 ,128 ,128 ,23 ,5.494 ,6.219 ,0.883 0 ,0 ,128 ,160 ,23 ,5.583 ,6.388 ,0.874 0 ,0 ,128 ,192 ,23 ,5.585 ,6.29 ,0.888 0 ,0 ,128 ,224 ,23 ,5.7 ,6.495 ,0.878 0 ,0 ,128 ,256 ,23 ,5.614 ,6.363 ,0.882 0 ,0 ,128 ,288 ,23 ,5.896 ,6.294 ,0.937 0 ,0 ,128 ,32 ,23 ,5.534 ,5.598 ,0.989 0 ,0 ,128 ,320 ,23 ,5.806 ,6.433 ,0.903 0 ,0 ,128 ,352 ,23 ,5.833 ,6.408 ,0.91 0 ,0 ,128 ,384 ,23 ,5.735 ,6.268 ,0.915 0 ,0 ,128 ,416 ,23 ,5.71 ,6.371 ,0.896 0 ,0 ,128 ,448 ,23 ,5.789 ,6.429 ,0.9 0 ,0 ,128 ,480 ,23 ,5.77 ,6.257 ,0.922 0 ,0 ,128 ,512 ,23 ,5.998 ,6.57 ,0.913 0 ,0 ,128 ,64 ,23 ,4.476 ,4.992 ,0.897 0 ,0 ,128 ,96 ,23 ,3.252 ,4.281 ,0.76 0 ,0 ,1280 ,1024 ,23 ,11.057 ,10.923 ,1.012 0 ,0 ,13 ,1 ,23 ,4.208 ,4.542 ,0.926 0 ,0 ,13 ,12 ,0 ,4.184 ,4.445 ,0.941 0 ,0 ,13 ,12 ,23 ,4.172 ,4.463 ,0.935 0 ,0 ,13 ,14 ,0 ,4.191 ,4.514 ,0.929 0 ,0 ,13 ,14 ,23 ,4.216 ,4.526 ,0.932 0 ,0 ,13 ,2 ,0 ,4.174 ,4.45 ,0.938 0 ,0 ,1312 ,1024 ,23 ,11.061 ,10.852 ,1.019 0 ,0 ,1344 ,1024 ,23 ,13.465 ,13.228 ,1.018 0 ,0 ,1376 ,1024 ,23 ,13.411 ,13.115 ,1.023 0 ,0 ,14 ,1 ,23 ,4.197 ,4.498 ,0.933 0 ,0 ,14 ,13 ,0 ,4.207 ,4.517 ,0.931 0 ,0 ,14 ,13 ,23 ,4.179 ,4.477 ,0.933 0 ,0 ,14 ,15 ,0 ,4.196 ,4.564 ,0.919 0 ,0 ,14 ,15 ,23 ,4.199 ,4.587 ,0.915 0 ,0 ,14 ,2 ,0 ,4.156 ,4.496 ,0.924 0 ,0 ,1408 ,1024 ,23 ,13.409 ,13.148 ,1.02 0 ,0 ,144 ,16 ,23 ,6.901 ,7.075 ,0.975 0 ,0 ,15 ,1 ,23 ,4.196 ,4.515 ,0.929 0 ,0 ,15 ,14 ,0 ,4.179 ,4.52 ,0.925 0 ,0 ,15 ,14 ,23 ,4.176 ,4.504 ,0.927 0 ,0 ,15 ,16 ,0 ,4.159 ,4.736 ,0.878 0 ,0 ,15 ,16 ,23 ,4.158 ,4.749 ,0.876 0 ,0 ,15 ,2 ,0 ,4.137 ,4.425 ,0.935 0 ,0 ,16 ,1 ,23 ,5.281 ,5.219 ,1.012 0 ,0 ,16 ,112 ,23 ,4.115 ,4.617 ,0.891 0 ,0 ,16 ,144 ,23 ,4.061 ,4.684 ,0.867 0 ,0 ,16 ,15 ,0 ,4.158 ,4.145 ,1.003 0 ,0 ,16 ,15 ,23 ,4.232 ,4.469 ,0.947 0 ,0 ,16 ,16 ,23 ,4.003 ,4.376 ,0.915 0 ,0 ,16 ,17 ,0 ,4.195 ,4.799 ,0.874 0 ,0 ,16 ,17 ,23 ,4.229 ,4.909 ,0.862 0 ,0 ,16 ,176 ,23 ,4.217 ,4.777 ,0.883 0 ,0 ,16 ,2 ,0 ,4.538 ,5.01 ,0.906 0 ,0 ,16 ,208 ,23 ,3.961 ,4.537 ,0.873 0 ,0 ,16 ,240 ,23 ,4.05 ,4.54 ,0.892 0 ,0 ,16 ,272 ,23 ,3.989 ,4.484 ,0.89 0 ,0 ,16 ,304 ,23 ,3.959 ,4.366 ,0.907 0 ,0 ,16 ,336 ,23 ,3.978 ,4.395 ,0.905 0 ,0 ,16 ,368 ,23 ,3.985 ,4.44 ,0.898 0 ,0 ,16 ,400 ,23 ,3.987 ,4.447 ,0.897 0 ,0 ,16 ,48 ,23 ,4.266 ,4.654 ,0.917 0 ,0 ,16 ,80 ,23 ,4.182 ,4.625 ,0.904 0 ,0 ,160 ,128 ,23 ,3.255 ,4.341 ,0.75 0 ,0 ,160 ,256 ,23 ,6.323 ,6.88 ,0.919 0 ,0 ,160 ,32 ,23 ,7.131 ,7.717 ,0.924 0 ,0 ,160 ,512 ,23 ,6.336 ,6.859 ,0.924 0 ,0 ,160 ,64 ,23 ,5.431 ,5.07 ,1.071 0 ,0 ,1664 ,2048 ,23 ,35.08 ,33.206 ,1.056 0 ,0 ,1696 ,2048 ,23 ,35.042 ,33.087 ,1.059 0 ,0 ,17 ,1 ,23 ,4.56 ,4.797 ,0.951 0 ,0 ,17 ,16 ,0 ,4.133 ,4.507 ,0.917 0 ,0 ,17 ,16 ,23 ,4.131 ,4.558 ,0.906 0 ,0 ,17 ,18 ,0 ,4.218 ,4.905 ,0.86 0 ,0 ,17 ,18 ,23 ,4.235 ,4.885 ,0.867 0 ,0 ,17 ,2 ,0 ,4.15 ,4.69 ,0.885 0 ,0 ,1728 ,2048 ,23 ,37.448 ,35.051 ,1.068 0 ,0 ,176 ,16 ,23 ,7.794 ,8.079 ,0.965 0 ,0 ,1760 ,2048 ,23 ,37.532 ,36.158 ,1.038 0 ,0 ,1792 ,2048 ,23 ,37.367 ,34.982 ,1.068 0 ,0 ,18 ,1 ,23 ,4.874 ,4.858 ,1.003 0 ,0 ,18 ,17 ,0 ,4.153 ,4.146 ,1.002 0 ,0 ,18 ,17 ,23 ,4.142 ,4.23 ,0.979 0 ,0 ,18 ,19 ,0 ,4.241 ,5.171 ,0.82 0 ,0 ,18 ,19 ,23 ,4.264 ,5.273 ,0.809 0 ,0 ,18 ,2 ,0 ,4.248 ,4.713 ,0.901 0 ,0 ,1824 ,2048 ,23 ,37.377 ,34.957 ,1.069 0 ,0 ,1856 ,2048 ,23 ,39.768 ,36.956 ,1.076 0 ,0 ,1888 ,2048 ,23 ,39.755 ,36.868 ,1.078 0 ,0 ,19 ,1 ,23 ,4.293 ,4.876 ,0.88 0 ,0 ,19 ,18 ,0 ,4.267 ,4.245 ,1.005 0 ,0 ,19 ,18 ,23 ,4.253 ,4.25 ,1.001 0 ,0 ,19 ,2 ,0 ,4.135 ,4.886 ,0.846 0 ,0 ,19 ,20 ,0 ,4.143 ,4.899 ,0.846 0 ,0 ,19 ,20 ,23 ,4.171 ,4.906 ,0.85 0 ,0 ,192 ,128 ,23 ,4.577 ,4.988 ,0.918 0 ,0 ,192 ,256 ,23 ,7.741 ,8.016 ,0.966 0 ,0 ,192 ,32 ,23 ,7.599 ,7.85 ,0.968 0 ,0 ,192 ,512 ,23 ,7.626 ,7.975 ,0.956 0 ,0 ,192 ,64 ,23 ,5.756 ,5.79 ,0.994 0 ,0 ,1920 ,2048 ,23 ,39.772 ,36.82 ,1.08 0 ,0 ,1952 ,2048 ,23 ,39.921 ,36.885 ,1.082 0 ,0 ,1984 ,2048 ,23 ,41.242 ,39.169 ,1.053 0 ,0 ,2 ,1 ,0 ,4.017 ,4.433 ,0.906 0 ,0 ,2 ,1 ,23 ,4.119 ,4.065 ,1.013 0 ,0 ,2 ,2 ,0 ,4.107 ,4.409 ,0.931 0 ,0 ,2 ,3 ,0 ,4.205 ,4.284 ,0.981 0 ,0 ,2 ,3 ,23 ,4.206 ,4.457 ,0.944 0 ,0 ,20 ,1 ,23 ,4.882 ,5.595 ,0.872 0 ,0 ,20 ,19 ,0 ,4.166 ,4.266 ,0.977 0 ,0 ,20 ,19 ,23 ,4.162 ,4.608 ,0.903 0 ,0 ,20 ,2 ,0 ,4.678 ,4.665 ,1.003 0 ,0 ,20 ,21 ,0 ,4.166 ,4.784 ,0.871 0 ,0 ,20 ,21 ,23 ,4.179 ,4.784 ,0.874 0 ,0 ,2016 ,2048 ,23 ,41.093 ,39.284 ,1.046 0 ,0 ,2048 ,1024 ,0 ,24.885 ,24.022 ,1.036 0 ,0 ,2048 ,1024 ,23 ,24.798 ,23.978 ,1.034 0 ,0 ,2048 ,128 ,0 ,40.325 ,37.87 ,1.065 0 ,0 ,2048 ,128 ,23 ,40.457 ,37.87 ,1.068 0 ,0 ,2048 ,1664 ,23 ,13.382 ,13.063 ,1.024 0 ,0 ,2048 ,1696 ,23 ,13.434 ,13.155 ,1.021 0 ,0 ,2048 ,1728 ,23 ,12.592 ,12.27 ,1.026 0 ,0 ,2048 ,1760 ,23 ,11.962 ,11.962 ,1.0 0 ,0 ,2048 ,1792 ,23 ,11.011 ,10.902 ,1.01 0 ,0 ,2048 ,1824 ,23 ,10.995 ,10.938 ,1.005 0 ,0 ,2048 ,1856 ,23 ,10.201 ,10.131 ,1.007 0 ,0 ,2048 ,1888 ,23 ,6.404 ,6.297 ,1.017 0 ,0 ,2048 ,1920 ,23 ,5.714 ,5.748 ,0.994 0 ,0 ,2048 ,1952 ,23 ,5.074 ,5.14 ,0.987 0 ,0 ,2048 ,1984 ,23 ,4.564 ,4.995 ,0.914 0 ,0 ,2048 ,2016 ,23 ,3.396 ,4.376 ,0.776 0 ,0 ,2048 ,2048 ,0 ,40.658 ,39.074 ,1.041 0 ,0 ,2048 ,2048 ,23 ,40.347 ,38.805 ,1.04 0 ,0 ,2048 ,2080 ,23 ,41.989 ,39.193 ,1.071 0 ,0 ,2048 ,2112 ,23 ,40.936 ,39.121 ,1.046 0 ,0 ,2048 ,2144 ,23 ,41.161 ,39.188 ,1.05 0 ,0 ,2048 ,2176 ,23 ,40.989 ,39.219 ,1.045 0 ,0 ,2048 ,2208 ,23 ,41.301 ,39.104 ,1.056 0 ,0 ,2048 ,2240 ,23 ,41.369 ,39.175 ,1.056 0 ,0 ,2048 ,2272 ,23 ,41.537 ,39.286 ,1.057 0 ,0 ,2048 ,2304 ,23 ,41.71 ,39.172 ,1.065 0 ,0 ,2048 ,2336 ,23 ,41.176 ,39.057 ,1.054 0 ,0 ,2048 ,2368 ,23 ,41.224 ,39.21 ,1.051 0 ,0 ,2048 ,2400 ,23 ,41.119 ,39.128 ,1.051 0 ,0 ,2048 ,2432 ,23 ,41.143 ,39.093 ,1.052 0 ,0 ,2048 ,256 ,0 ,38.247 ,35.695 ,1.071 0 ,0 ,2048 ,256 ,23 ,38.579 ,35.723 ,1.08 0 ,0 ,2048 ,32 ,0 ,42.099 ,38.795 ,1.085 0 ,0 ,2048 ,32 ,23 ,42.233 ,38.449 ,1.098 0 ,0 ,2048 ,512 ,0 ,34.046 ,31.725 ,1.073 0 ,0 ,2048 ,512 ,23 ,34.009 ,31.905 ,1.066 0 ,0 ,2048 ,64 ,0 ,40.225 ,37.885 ,1.062 0 ,0 ,2048 ,64 ,23 ,40.111 ,37.916 ,1.058 0 ,0 ,208 ,16 ,23 ,8.706 ,8.964 ,0.971 0 ,0 ,2080 ,2048 ,23 ,3.357 ,4.439 ,0.756 0 ,0 ,21 ,1 ,23 ,4.667 ,5.023 ,0.929 0 ,0 ,21 ,2 ,0 ,4.458 ,4.805 ,0.928 0 ,0 ,21 ,20 ,0 ,4.133 ,4.503 ,0.918 0 ,0 ,21 ,20 ,23 ,4.095 ,4.581 ,0.894 0 ,0 ,21 ,22 ,0 ,4.178 ,4.819 ,0.867 0 ,0 ,21 ,22 ,23 ,4.393 ,4.926 ,0.892 0 ,0 ,2112 ,2048 ,23 ,4.632 ,5.076 ,0.913 0 ,0 ,2144 ,2048 ,23 ,5.248 ,5.21 ,1.007 0 ,0 ,2176 ,2048 ,23 ,5.902 ,5.979 ,0.987 0 ,0 ,22 ,1 ,23 ,4.42 ,4.878 ,0.906 0 ,0 ,22 ,2 ,0 ,4.384 ,4.881 ,0.898 0 ,0 ,22 ,21 ,0 ,4.124 ,4.492 ,0.918 0 ,0 ,22 ,21 ,23 ,4.122 ,4.854 ,0.849 0 ,0 ,22 ,23 ,0 ,4.153 ,4.901 ,0.847 0 ,0 ,22 ,23 ,23 ,4.231 ,5.081 ,0.833 0 ,0 ,2208 ,2048 ,23 ,6.535 ,6.545 ,0.998 0 ,0 ,224 ,128 ,23 ,5.022 ,5.113 ,0.982 0 ,0 ,224 ,256 ,23 ,8.421 ,8.514 ,0.989 0 ,0 ,224 ,32 ,23 ,8.467 ,8.063 ,1.05 0 ,0 ,224 ,512 ,23 ,8.37 ,8.561 ,0.978 0 ,0 ,224 ,64 ,23 ,6.351 ,6.307 ,1.007 0 ,0 ,2240 ,2048 ,23 ,11.274 ,11.262 ,1.001 0 ,0 ,2272 ,2048 ,23 ,11.408 ,12.951 ,0.881 0 ,0 ,23 ,1 ,23 ,4.669 ,4.752 ,0.983 0 ,0 ,23 ,2 ,0 ,4.335 ,4.581 ,0.946 0 ,0 ,23 ,22 ,0 ,4.244 ,4.494 ,0.944 0 ,0 ,23 ,22 ,23 ,4.233 ,4.686 ,0.903 0 ,0 ,23 ,24 ,0 ,4.282 ,5.074 ,0.844 0 ,0 ,23 ,24 ,23 ,4.348 ,5.185 ,0.839 0 ,0 ,2304 ,2048 ,23 ,11.17 ,11.033 ,1.012 0 ,0 ,2336 ,2048 ,23 ,11.212 ,11.015 ,1.018 0 ,0 ,2368 ,2048 ,23 ,13.644 ,13.338 ,1.023 0 ,0 ,24 ,1 ,23 ,4.491 ,4.865 ,0.923 0 ,0 ,24 ,2 ,0 ,4.392 ,4.602 ,0.954 0 ,0 ,24 ,23 ,0 ,4.367 ,4.125 ,1.059 0 ,0 ,24 ,23 ,23 ,4.345 ,4.43 ,0.981 0 ,0 ,24 ,25 ,0 ,4.235 ,4.93 ,0.859 0 ,0 ,24 ,25 ,23 ,4.256 ,4.982 ,0.854 0 ,0 ,240 ,16 ,23 ,9.724 ,9.198 ,1.057 0 ,0 ,2400 ,2048 ,23 ,13.547 ,13.255 ,1.022 0 ,0 ,2432 ,2048 ,23 ,13.511 ,13.073 ,1.034 0 ,0 ,25 ,1 ,23 ,4.577 ,4.864 ,0.941 0 ,0 ,25 ,2 ,0 ,4.484 ,4.924 ,0.911 0 ,0 ,25 ,24 ,0 ,4.232 ,4.232 ,1.0 0 ,0 ,25 ,24 ,23 ,4.258 ,4.546 ,0.936 0 ,0 ,25 ,26 ,0 ,4.21 ,5.123 ,0.822 0 ,0 ,25 ,26 ,23 ,4.275 ,5.077 ,0.842 0 ,0 ,256 ,1 ,0 ,9.374 ,9.03 ,1.038 0 ,0 ,256 ,1 ,23 ,9.42 ,9.104 ,1.035 0 ,0 ,256 ,128 ,23 ,5.885 ,5.754 ,1.023 0 ,0 ,256 ,160 ,23 ,5.017 ,5.037 ,0.996 0 ,0 ,256 ,192 ,23 ,4.491 ,5.003 ,0.898 0 ,0 ,256 ,2 ,0 ,9.37 ,9.08 ,1.032 0 ,0 ,256 ,2 ,23 ,9.393 ,9.14 ,1.028 0 ,0 ,256 ,224 ,23 ,3.294 ,4.214 ,0.782 0 ,0 ,256 ,256 ,23 ,9.583 ,9.046 ,1.059 0 ,0 ,256 ,288 ,23 ,9.911 ,9.147 ,1.084 0 ,0 ,256 ,3 ,0 ,9.49 ,9.037 ,1.05 0 ,0 ,256 ,3 ,23 ,9.481 ,9.085 ,1.044 0 ,0 ,256 ,32 ,23 ,8.183 ,8.242 ,0.993 0 ,0 ,256 ,320 ,23 ,10.085 ,9.136 ,1.104 0 ,0 ,256 ,352 ,23 ,9.925 ,9.159 ,1.084 0 ,0 ,256 ,384 ,23 ,9.788 ,9.133 ,1.072 0 ,0 ,256 ,4 ,0 ,9.491 ,9.113 ,1.042 0 ,0 ,256 ,4 ,23 ,9.462 ,9.09 ,1.041 0 ,0 ,256 ,416 ,23 ,9.473 ,9.202 ,1.029 0 ,0 ,256 ,448 ,23 ,9.785 ,9.19 ,1.065 0 ,0 ,256 ,480 ,23 ,9.976 ,9.139 ,1.092 0 ,0 ,256 ,5 ,0 ,9.455 ,9.037 ,1.046 0 ,0 ,256 ,5 ,23 ,9.456 ,9.109 ,1.038 0 ,0 ,256 ,512 ,23 ,10.303 ,9.137 ,1.128 0 ,0 ,256 ,544 ,23 ,9.939 ,9.129 ,1.089 0 ,0 ,256 ,576 ,23 ,9.972 ,9.208 ,1.083 0 ,0 ,256 ,6 ,0 ,9.499 ,9.108 ,1.043 0 ,0 ,256 ,6 ,23 ,9.527 ,9.122 ,1.044 0 ,0 ,256 ,608 ,23 ,10.028 ,9.077 ,1.105 0 ,0 ,256 ,64 ,23 ,7.529 ,7.676 ,0.981 0 ,0 ,256 ,640 ,23 ,9.809 ,9.212 ,1.065 0 ,0 ,256 ,7 ,0 ,9.347 ,9.11 ,1.026 0 ,0 ,256 ,7 ,23 ,9.335 ,9.097 ,1.026 0 ,0 ,256 ,96 ,23 ,6.396 ,6.311 ,1.013 0 ,0 ,26 ,1 ,23 ,4.898 ,4.83 ,1.014 0 ,0 ,26 ,2 ,0 ,4.35 ,4.506 ,0.965 0 ,0 ,26 ,25 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,4.552 ,0.907 7 ,0 ,192 ,224 ,0 ,8.453 ,8.551 ,0.989 7 ,0 ,192 ,224 ,23 ,8.44 ,8.569 ,0.985 7 ,0 ,256 ,224 ,0 ,3.235 ,4.249 ,0.761 7 ,0 ,256 ,224 ,23 ,3.231 ,4.29 ,0.753 7 ,0 ,256 ,64 ,0 ,8.219 ,8.284 ,0.992 7 ,0 ,256 ,64 ,23 ,8.332 ,8.302 ,1.004 7 ,0 ,256 ,7 ,0 ,10.106 ,9.71 ,1.041 7 ,0 ,256 ,7 ,23 ,10.066 ,9.764 ,1.031 7 ,0 ,512 ,224 ,0 ,12.335 ,12.171 ,1.013 7 ,0 ,512 ,224 ,23 ,12.275 ,12.182 ,1.008 7 ,0 ,6 ,7 ,0 ,4.185 ,4.495 ,0.931 7 ,0 ,6 ,7 ,23 ,4.164 ,4.44 ,0.938 7 ,0 ,8 ,7 ,0 ,4.184 ,4.505 ,0.929 7 ,0 ,8 ,7 ,23 ,4.171 ,4.415 ,0.945 7 ,1 ,192 ,224 ,0 ,8.406 ,8.524 ,0.986 7 ,1 ,192 ,224 ,23 ,8.382 ,8.572 ,0.978 7 ,1 ,256 ,224 ,0 ,9.559 ,9.064 ,1.055 7 ,1 ,256 ,224 ,23 ,9.579 ,9.117 ,1.051 7 ,1 ,256 ,64 ,0 ,5.316 ,5.677 ,0.936 7 ,1 ,256 ,64 ,23 ,5.332 ,5.502 ,0.969 7 ,1 ,256 ,7 ,0 ,3.386 ,4.357 ,0.777 7 ,1 ,256 ,7 ,23 ,3.34 ,4.305 ,0.776 7 ,1 ,512 ,224 ,0 ,11.153 ,11.117 ,1.003 7 ,1 ,512 ,224 ,23 ,11.268 ,11.236 ,1.003 7 ,1 ,6 ,7 ,0 ,4.146 ,4.433 ,0.935 7 ,1 ,6 ,7 ,23 ,4.13 ,4.414 ,0.936 7 ,1 ,8 ,7 ,0 ,4.093 ,4.547 ,0.9 7 ,1 ,8 ,7 ,23 ,4.133 ,4.452 ,0.928 8 ,0 ,7 ,8 ,0 ,4.17 ,4.412 ,0.945 8 ,0 ,7 ,8 ,23 ,4.182 ,4.49 ,0.931 8 ,0 ,9 ,8 ,0 ,4.195 ,4.183 ,1.003 8 ,0 ,9 ,8 ,23 ,4.318 ,4.436 ,0.973 8 ,1 ,7 ,8 ,0 ,4.136 ,4.474 ,0.925 8 ,1 ,7 ,8 ,23 ,4.143 ,4.439 ,0.933 8 ,1 ,9 ,8 ,0 ,4.155 ,4.435 ,0.937 8 ,1 ,9 ,8 ,23 ,4.154 ,4.462 ,0.931 9 ,0 ,10 ,9 ,0 ,4.159 ,4.139 ,1.005 9 ,0 ,10 ,9 ,23 ,4.166 ,4.519 ,0.922 9 ,0 ,8 ,9 ,0 ,4.222 ,4.596 ,0.919 9 ,0 ,8 ,9 ,23 ,4.175 ,4.51 ,0.926 9 ,1 ,10 ,9 ,0 ,4.143 ,4.474 ,0.926 9 ,1 ,10 ,9 ,23 ,4.155 ,4.534 ,0.916 9 ,1 ,8 ,9 ,0 ,4.168 ,4.554 ,0.915 9 ,1 ,8 ,9 ,23 ,4.172 ,4.452 ,0.937 0.9494839567637894
diff --git a/sysdeps/x86_64/multiarch/memrchr-evex.S b/sysdeps/x86_64/multiarch/memrchr-evex.S index 550b328c5a..dbcf52808f 100644 --- a/sysdeps/x86_64/multiarch/memrchr-evex.S +++ b/sysdeps/x86_64/multiarch/memrchr-evex.S @@ -21,17 +21,19 @@ #if ISA_SHOULD_BUILD (4) # include <sysdep.h> -# include "x86-evex256-vecs.h" -# if VEC_SIZE != 32 -# error "VEC_SIZE != 32 unimplemented" + +# ifndef VEC_SIZE +# include "x86-evex256-vecs.h" # endif +# include "reg-macros.h" + # ifndef MEMRCHR -# define MEMRCHR __memrchr_evex +# define MEMRCHR __memrchr_evex # endif -# define PAGE_SIZE 4096 -# define VMMMATCH VMM(0) +# define PAGE_SIZE 4096 +# define VMATCH VMM(0) .section SECTION(.text), "ax", @progbits ENTRY_P2ALIGN(MEMRCHR, 6) @@ -43,294 +45,402 @@ ENTRY_P2ALIGN(MEMRCHR, 6) # endif jz L(zero_0) - /* Get end pointer. Minus one for two reasons. 1) It is necessary for a - correct page cross check and 2) it correctly sets up end ptr to be - subtract by lzcnt aligned. */ + /* Get end pointer. Minus one for three reasons. 1) It is + necessary for a correct page cross check and 2) it correctly + sets up end ptr to be subtract by lzcnt aligned. 3) it is a + necessary step in aligning ptr. */ leaq -1(%rdi, %rdx), %rax - vpbroadcastb %esi, %VMMMATCH + vpbroadcastb %esi, %VMATCH /* Check if we can load 1x VEC without cross a page. */ testl $(PAGE_SIZE - VEC_SIZE), %eax jz L(page_cross) - /* Don't use rax for pointer here because EVEX has better encoding with - offset % VEC_SIZE == 0. */ - vpcmpb $0, -(VEC_SIZE)(%rdi, %rdx), %VMMMATCH, %k0 - kmovd %k0, %ecx - - /* Fall through for rdx (len) <= VEC_SIZE (expect small sizes). */ - cmpq $VEC_SIZE, %rdx - ja L(more_1x_vec) -L(ret_vec_x0_test): - - /* If ecx is zero (no matches) lzcnt will set it 32 (VEC_SIZE) which - will guarantee edx (len) is less than it. */ - lzcntl %ecx, %ecx - cmpl %ecx, %edx - jle L(zero_0) - subq %rcx, %rax + /* Don't use rax for pointer here because EVEX has better + encoding with offset % VEC_SIZE == 0. */ + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rdx), %VMATCH, %k0 + KMOV %k0, %VRCX + + /* If rcx is zero then lzcnt -> VEC_SIZE. NB: there is a + already a dependency between rcx and rsi so no worries about + false-dep here. */ + lzcnt %VRCX, %VRSI + /* If rdx <= rsi then either 1) rcx was non-zero (there was a + match) but it was out of bounds or 2) rcx was zero and rdx + was <= VEC_SIZE so we are done scanning. */ + cmpq %rsi, %rdx + /* NB: Use branch to return zero/non-zero. Common usage will + branch on result of function (if return is null/non-null). + This branch can be used to predict the ensuing one so there + is no reason to extend the data-dependency with cmovcc. */ + jbe L(zero_0) + + /* If rcx is zero then len must be > RDX, otherwise since we + already tested len vs lzcnt(rcx) (in rsi) we are good to + return this match. */ + test %VRCX, %VRCX + jz L(more_1x_vec) + subq %rsi, %rax ret - /* Fits in aligning bytes of first cache line. */ + /* Fits in aligning bytes of first cache line for VEC_SIZE == + 32. */ +# if VEC_SIZE == 32 + .p2align 4,, 2 L(zero_0): xorl %eax, %eax ret - - .p2align 4,, 9 -L(ret_vec_x0_dec): - decq %rax -L(ret_vec_x0): - lzcntl %ecx, %ecx - subq %rcx, %rax - ret +# endif .p2align 4,, 10 L(more_1x_vec): - testl %ecx, %ecx - jnz L(ret_vec_x0) - /* Align rax (pointer to string). */ andq $-VEC_SIZE, %rax - +L(page_cross_continue): /* Recompute length after aligning. */ - movq %rax, %rdx + subq %rdi, %rax - /* Need no matter what. */ - vpcmpb $0, -(VEC_SIZE)(%rax), %VMMMATCH, %k0 - kmovd %k0, %ecx - - subq %rdi, %rdx - - cmpq $(VEC_SIZE * 2), %rdx + cmpq $(VEC_SIZE * 2), %rax ja L(more_2x_vec) + L(last_2x_vec): + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rax), %VMATCH, %k0 + KMOV %k0, %VRCX - /* Must dec rax because L(ret_vec_x0_test) expects it. */ - decq %rax - cmpl $VEC_SIZE, %edx - jbe L(ret_vec_x0_test) + test %VRCX, %VRCX + jnz L(ret_vec_x0_test) - testl %ecx, %ecx - jnz L(ret_vec_x0) + /* If VEC_SIZE == 64 need to subtract because lzcntq won't + implicitly add VEC_SIZE to match position. */ +# if VEC_SIZE == 64 + subl $VEC_SIZE, %eax +# else + cmpb $VEC_SIZE, %al +# endif + jle L(zero_2) - /* Don't use rax for pointer here because EVEX has better encoding with - offset % VEC_SIZE == 0. */ - vpcmpb $0, -(VEC_SIZE * 2)(%rdi, %rdx), %VMMMATCH, %k0 - kmovd %k0, %ecx - /* NB: 64-bit lzcnt. This will naturally add 32 to position. */ + /* We adjusted rax (length) for VEC_SIZE == 64 so need seperate + offsets. */ +# if VEC_SIZE == 64 + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rax), %VMATCH, %k0 +# else + vpcmpeqb (VEC_SIZE * -2)(%rdi, %rax), %VMATCH, %k0 +# endif + KMOV %k0, %VRCX + /* NB: 64-bit lzcnt. This will naturally add 32 to position for + VEC_SIZE == 32. */ lzcntq %rcx, %rcx - cmpl %ecx, %edx - jle L(zero_0) - subq %rcx, %rax - ret - - /* Inexpensive place to put this regarding code size / target alignments - / ICache NLP. Necessary for 2-byte encoding of jump to page cross - case which in turn is necessary for hot path (len <= VEC_SIZE) to fit - in first cache line. */ -L(page_cross): - movq %rax, %rsi - andq $-VEC_SIZE, %rsi - vpcmpb $0, (%rsi), %VMMMATCH, %k0 - kmovd %k0, %r8d - /* Shift out negative alignment (because we are starting from endptr and - working backwards). */ - movl %eax, %ecx - /* notl because eax already has endptr - 1. (-x = ~(x - 1)). */ - notl %ecx - shlxl %ecx, %r8d, %ecx - cmpq %rdi, %rsi - ja L(more_1x_vec) - lzcntl %ecx, %ecx - cmpl %ecx, %edx - jle L(zero_1) - subq %rcx, %rax + subl %ecx, %eax + ja L(first_vec_x1_ret) + /* If VEC_SIZE == 64 put L(zero_0) here as we can't fit in the + first cache line (this is the second cache line). */ +# if VEC_SIZE == 64 +L(zero_0): +# endif +L(zero_2): + xorl %eax, %eax ret - /* Continue creating zero labels that fit in aligning bytes and get - 2-byte encoding / are in the same cache line as condition. */ -L(zero_1): - xorl %eax, %eax + /* NB: Fits in aligning bytes before next cache line for + VEC_SIZE == 32. For VEC_SIZE == 64 this is attached to + L(first_vec_x0_test). */ +# if VEC_SIZE == 32 +L(first_vec_x1_ret): + leaq -1(%rdi, %rax), %rax ret +# endif - .p2align 4,, 8 -L(ret_vec_x1): - /* This will naturally add 32 to position. */ - bsrl %ecx, %ecx - leaq -(VEC_SIZE * 2)(%rcx, %rax), %rax + .p2align 4,, 6 +L(ret_vec_x0_test): + lzcnt %VRCX, %VRCX + subl %ecx, %eax + jle L(zero_2) +# if VEC_SIZE == 64 + /* Reuse code at the end of L(ret_vec_x0_test) as we can't fit + L(first_vec_x1_ret) in the same cache line as its jmp base + so we might as well save code size. */ +L(first_vec_x1_ret): +# endif + leaq -1(%rdi, %rax), %rax ret - .p2align 4,, 8 + .p2align 4,, 6 +L(loop_last_4x_vec): + /* Compute remaining length. */ + subl %edi, %eax +L(last_4x_vec): + cmpl $(VEC_SIZE * 2), %eax + jle L(last_2x_vec) +# if VEC_SIZE == 32 + /* Only align for VEC_SIZE == 32. For VEC_SIZE == 64 we need + the spare bytes to align the loop properly. */ + .p2align 4,, 10 +# endif L(more_2x_vec): - testl %ecx, %ecx - jnz L(ret_vec_x0_dec) - vpcmpb $0, -(VEC_SIZE * 2)(%rax), %VMMMATCH, %k0 - kmovd %k0, %ecx - testl %ecx, %ecx - jnz L(ret_vec_x1) + /* Length > VEC_SIZE * 2 so check the first 2x VEC for match and + return if either hit. */ + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rax), %VMATCH, %k0 + KMOV %k0, %VRCX + + test %VRCX, %VRCX + jnz L(first_vec_x0) + + vpcmpeqb (VEC_SIZE * -2)(%rdi, %rax), %VMATCH, %k0 + KMOV %k0, %VRCX + test %VRCX, %VRCX + jnz L(first_vec_x1) /* Need no matter what. */ - vpcmpb $0, -(VEC_SIZE * 3)(%rax), %VMMMATCH, %k0 - kmovd %k0, %ecx + vpcmpeqb (VEC_SIZE * -3)(%rdi, %rax), %VMATCH, %k0 + KMOV %k0, %VRCX - subq $(VEC_SIZE * 4), %rdx + /* Check if we are near the end. */ + subq $(VEC_SIZE * 4), %rax ja L(more_4x_vec) - cmpl $(VEC_SIZE * -1), %edx - jle L(ret_vec_x2_test) -L(last_vec): - testl %ecx, %ecx - jnz L(ret_vec_x2) + test %VRCX, %VRCX + jnz L(first_vec_x2_test) + /* Adjust length for final check and check if we are at the end. + */ + addl $(VEC_SIZE * 1), %eax + jle L(zero_1) - /* Need no matter what. */ - vpcmpb $0, -(VEC_SIZE * 4)(%rax), %VMMMATCH, %k0 - kmovd %k0, %ecx - lzcntl %ecx, %ecx - subq $(VEC_SIZE * 3 + 1), %rax - subq %rcx, %rax - cmpq %rax, %rdi - ja L(zero_1) + vpcmpeqb (VEC_SIZE * -1)(%rdi, %rax), %VMATCH, %k0 + KMOV %k0, %VRCX + + lzcnt %VRCX, %VRCX + subl %ecx, %eax + ja L(first_vec_x3_ret) +L(zero_1): + xorl %eax, %eax + ret +L(first_vec_x3_ret): + leaq -1(%rdi, %rax), %rax ret - .p2align 4,, 8 -L(ret_vec_x2_test): - lzcntl %ecx, %ecx - subq $(VEC_SIZE * 2 + 1), %rax - subq %rcx, %rax - cmpq %rax, %rdi - ja L(zero_1) + .p2align 4,, 6 +L(first_vec_x2_test): + /* Must adjust length before check. */ + subl $-(VEC_SIZE * 2 - 1), %eax + lzcnt %VRCX, %VRCX + subl %ecx, %eax + jl L(zero_4) + addq %rdi, %rax ret - .p2align 4,, 8 -L(ret_vec_x2): - bsrl %ecx, %ecx - leaq -(VEC_SIZE * 3)(%rcx, %rax), %rax + + .p2align 4,, 10 +L(first_vec_x0): + bsr %VRCX, %VRCX + leaq (VEC_SIZE * -1)(%rdi, %rax), %rax + addq %rcx, %rax ret - .p2align 4,, 8 -L(ret_vec_x3): - bsrl %ecx, %ecx - leaq -(VEC_SIZE * 4)(%rcx, %rax), %rax + /* Fits unobtrusively here. */ +L(zero_4): + xorl %eax, %eax + ret + + .p2align 4,, 10 +L(first_vec_x1): + bsr %VRCX, %VRCX + leaq (VEC_SIZE * -2)(%rdi, %rax), %rax + addq %rcx, %rax ret .p2align 4,, 8 +L(first_vec_x3): + bsr %VRCX, %VRCX + addq %rdi, %rax + addq %rcx, %rax + ret + + .p2align 4,, 6 +L(first_vec_x2): + bsr %VRCX, %VRCX + leaq (VEC_SIZE * 1)(%rdi, %rax), %rax + addq %rcx, %rax + ret + + .p2align 4,, 2 L(more_4x_vec): - testl %ecx, %ecx - jnz L(ret_vec_x2) + test %VRCX, %VRCX + jnz L(first_vec_x2) - vpcmpb $0, -(VEC_SIZE * 4)(%rax), %VMMMATCH, %k0 - kmovd %k0, %ecx + vpcmpeqb (%rdi, %rax), %VMATCH, %k0 + KMOV %k0, %VRCX - testl %ecx, %ecx - jnz L(ret_vec_x3) + test %VRCX, %VRCX + jnz L(first_vec_x3) /* Check if near end before re-aligning (otherwise might do an unnecessary loop iteration). */ - addq $-(VEC_SIZE * 4), %rax - cmpq $(VEC_SIZE * 4), %rdx + cmpq $(VEC_SIZE * 4), %rax jbe L(last_4x_vec) - decq %rax - andq $-(VEC_SIZE * 4), %rax - movq %rdi, %rdx - /* Get endptr for loop in rdx. NB: Can't just do while rax > rdi because - lengths that overflow can be valid and break the comparison. */ - andq $-(VEC_SIZE * 4), %rdx + + /* NB: We setup the loop to NOT use index-address-mode for the + buffer. This costs some instructions & code size but avoids + stalls due to unlaminated micro-fused instructions (as used + in the loop) from being forced to issue in the same group + (essentially narrowing the backend width). */ + + /* Get endptr for loop in rdx. NB: Can't just do while rax > rdi + because lengths that overflow can be valid and break the + comparison. */ +# if VEC_SIZE == 64 + /* Use rdx as intermediate to compute rax, this gets us imm8 + encoding which just allows the L(more_4x_vec) block to fit + in 1 cache-line. */ + leaq (VEC_SIZE * 4)(%rdi), %rdx + leaq (VEC_SIZE * -1)(%rdx, %rax), %rax + + /* No evex machine has partial register stalls. This can be + replaced with: `andq $(VEC_SIZE * -4), %rax/%rdx` if that + changes. */ + xorb %al, %al + xorb %dl, %dl +# else + leaq (VEC_SIZE * 3)(%rdi, %rax), %rax + andq $(VEC_SIZE * -4), %rax + leaq (VEC_SIZE * 4)(%rdi), %rdx + andq $(VEC_SIZE * -4), %rdx +# endif + .p2align 4 L(loop_4x_vec): - /* Store 1 were not-equals and 0 where equals in k1 (used to mask later - on). */ - vpcmpb $4, (VEC_SIZE * 3)(%rax), %VMMMATCH, %k1 + /* NB: We could do the same optimization here as we do for + memchr/rawmemchr by using VEX encoding in the loop for access + to VEX vpcmpeqb + vpternlogd. Since memrchr is not as hot as + memchr it may not be worth the extra code size, but if the + need arises it an easy ~15% perf improvement to the loop. */ + + cmpq %rdx, %rax + je L(loop_last_4x_vec) + /* Store 1 were not-equals and 0 where equals in k1 (used to + mask later on). */ + vpcmpb $4, (VEC_SIZE * -1)(%rax), %VMATCH, %k1 /* VEC(2/3) will have zero-byte where we found a CHAR. */ - vpxorq (VEC_SIZE * 2)(%rax), %VMMMATCH, %VMM(2) - vpxorq (VEC_SIZE * 1)(%rax), %VMMMATCH, %VMM(3) - vpcmpb $0, (VEC_SIZE * 0)(%rax), %VMMMATCH, %k4 + vpxorq (VEC_SIZE * -2)(%rax), %VMATCH, %VMM(2) + vpxorq (VEC_SIZE * -3)(%rax), %VMATCH, %VMM(3) + vpcmpeqb (VEC_SIZE * -4)(%rax), %VMATCH, %k4 - /* Combine VEC(2/3) with min and maskz with k1 (k1 has zero bit where - CHAR is found and VEC(2/3) have zero-byte where CHAR is found. */ + /* Combine VEC(2/3) with min and maskz with k1 (k1 has zero bit + where CHAR is found and VEC(2/3) have zero-byte where CHAR + is found. */ vpminub %VMM(2), %VMM(3), %VMM(3){%k1}{z} vptestnmb %VMM(3), %VMM(3), %k2 - /* Any 1s and we found CHAR. */ - kortestd %k2, %k4 - jnz L(loop_end) - addq $-(VEC_SIZE * 4), %rax - cmpq %rdx, %rax - jne L(loop_4x_vec) - /* Need to re-adjust rdx / rax for L(last_4x_vec). */ - subq $-(VEC_SIZE * 4), %rdx - movq %rdx, %rax - subl %edi, %edx -L(last_4x_vec): + /* Any 1s and we found CHAR. */ + KORTEST %k2, %k4 + jz L(loop_4x_vec) + - /* Used no matter what. */ - vpcmpb $0, (VEC_SIZE * -1)(%rax), %VMMMATCH, %k0 - kmovd %k0, %ecx + /* K1 has non-matches for first VEC. inc; jz will overflow rcx + iff all bytes where non-matches. */ + KMOV %k1, %VRCX + inc %VRCX + jnz L(first_vec_x0_end) - cmpl $(VEC_SIZE * 2), %edx - jbe L(last_2x_vec) + vptestnmb %VMM(2), %VMM(2), %k0 + KMOV %k0, %VRCX + test %VRCX, %VRCX + jnz L(first_vec_x1_end) + KMOV %k2, %VRCX + + /* Seperate logic for VEC_SIZE == 64 and VEC_SIZE == 32 for + returning last 2x VEC. For VEC_SIZE == 64 we test each VEC + individually, for VEC_SIZE == 32 we combine them in a single + 64-bit GPR. */ +# if VEC_SIZE == 64 + test %VRCX, %VRCX + jnz L(first_vec_x2_end) + KMOV %k4, %VRCX +# else + /* Combine last 2 VEC matches for VEC_SIZE == 32. If rcx (from + VEC(3)) is zero (no CHAR in VEC(3)) then it won't affect the + result in rsi (from VEC(4)). If rcx is non-zero then CHAR in + VEC(3) and bsrq will use that position. */ + KMOV %k4, %VRSI + salq $32, %rcx + orq %rsi, %rcx +# endif + bsrq %rcx, %rcx + addq %rcx, %rax + ret - testl %ecx, %ecx - jnz L(ret_vec_x0_dec) + .p2align 4,, 4 +L(first_vec_x0_end): + /* rcx has 1s at non-matches so we need to `not` it. We used + `inc` to test if zero so use `neg` to complete the `not` so + the last 1 bit represent a match. NB: (-x + 1 == ~x). */ + neg %VRCX + bsr %VRCX, %VRCX + leaq (VEC_SIZE * 3)(%rcx, %rax), %rax + ret + .p2align 4,, 10 +L(first_vec_x1_end): + bsr %VRCX, %VRCX + leaq (VEC_SIZE * 2)(%rcx, %rax), %rax + ret - vpcmpb $0, (VEC_SIZE * -2)(%rax), %VMMMATCH, %k0 - kmovd %k0, %ecx +# if VEC_SIZE == 64 + /* Since we can't combine the last 2x VEC for VEC_SIZE == 64 + need return label for it. */ + .p2align 4,, 4 +L(first_vec_x2_end): + bsr %VRCX, %VRCX + leaq (VEC_SIZE * 1)(%rcx, %rax), %rax + ret +# endif - testl %ecx, %ecx - jnz L(ret_vec_x1) - /* Used no matter what. */ - vpcmpb $0, (VEC_SIZE * -3)(%rax), %VMMMATCH, %k0 - kmovd %k0, %ecx + .p2align 4,, 4 +L(page_cross): + /* only lower bits of eax[log2(VEC_SIZE):0] are set so we can + use movzbl to get the amount of bytes we are checking here. + */ + movzbl %al, %ecx + andq $-VEC_SIZE, %rax + vpcmpeqb (%rax), %VMATCH, %k0 + KMOV %k0, %VRSI - cmpl $(VEC_SIZE * 3), %edx - ja L(last_vec) + /* eax was comptued as %rdi + %rdx - 1 so need to add back 1 + here. */ + leal 1(%rcx), %r8d - lzcntl %ecx, %ecx - subq $(VEC_SIZE * 2 + 1), %rax - subq %rcx, %rax - cmpq %rax, %rdi - jbe L(ret_1) + /* Invert ecx to get shift count for byte matches out of range. + */ + notl %ecx + shlx %VRCX, %VRSI, %VRSI + + /* if r8 < rdx then the entire [buf, buf + len] is handled in + the page cross case. NB: we can't use the trick here we use + in the non page-cross case because we aren't checking full + VEC_SIZE. */ + cmpq %r8, %rdx + ja L(page_cross_check) + lzcnt %VRSI, %VRSI + subl %esi, %edx + ja L(page_cross_ret) xorl %eax, %eax -L(ret_1): ret - .p2align 4,, 6 -L(loop_end): - kmovd %k1, %ecx - notl %ecx - testl %ecx, %ecx - jnz L(ret_vec_x0_end) +L(page_cross_check): + test %VRSI, %VRSI + jz L(page_cross_continue) - vptestnmb %VMM(2), %VMM(2), %k0 - kmovd %k0, %ecx - testl %ecx, %ecx - jnz L(ret_vec_x1_end) - - kmovd %k2, %ecx - kmovd %k4, %esi - /* Combine last 2 VEC matches. If ecx (VEC3) is zero (no CHAR in VEC3) - then it won't affect the result in esi (VEC4). If ecx is non-zero - then CHAR in VEC3 and bsrq will use that position. */ - salq $32, %rcx - orq %rsi, %rcx - bsrq %rcx, %rcx - addq %rcx, %rax - ret - .p2align 4,, 4 -L(ret_vec_x0_end): - addq $(VEC_SIZE), %rax -L(ret_vec_x1_end): - bsrl %ecx, %ecx - leaq (VEC_SIZE * 2)(%rax, %rcx), %rax + lzcnt %VRSI, %VRSI + subl %esi, %edx +L(page_cross_ret): + leaq -1(%rdi, %rdx), %rax ret - END(MEMRCHR) #endif