| Message ID | 20221018024901.3381469-2-goldstein.w.n@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1,1/7] x86: Optimize memchr-evex.S and implement with VMM headers | expand |
On Mon, Oct 17, 2022 at 7:49 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote: > > Size Optimizations: > 1. Condence hot path for better cache-locality. > - This is most impact for strchrnul where the logic strings with > len <= VEC_SIZE or with a match in the first VEC no fits entirely > in the first cache line. > 2. Reuse common targets in first 4x VEC and after the loop. > 3. Don't align targets so aggressively if it doesn't change the number > of fetch blocks it will require and put more care in avoiding the > case where targets unnecessarily split cache lines. > 4. Align the loop better for DSB/LSD > 5. Use more code-size efficient instructions. > - tzcnt ... -> bsf ... > - vpcmpb $0 ... -> vpcmpeq ... > 6. Align labels less aggressively, especially if it doesn't save fetch > blocks / causes the basic-block to span extra cache-lines. > > Code Size Changes: > strchr-evex.S : -63 bytes > strchrnul-evex.S: -48 bytes > > Net perf changes: > Reported as geometric mean of all improvements / regressions from N=10 > runs of the benchtests. Value as New Time / Old Time so < 1.0 is > improvement and 1.0 is regression. > > strchr-evex.S (Fixed) : 0.971 > strchr-evex.S (Rand) : 0.932 > strchrnul-evex.S : 0.965 > > Full results attached in email. > > Full check passes on x86-64. > --- > sysdeps/x86_64/multiarch/strchr-evex.S | 558 +++++++++++++++---------- > 1 file changed, 340 insertions(+), 218 deletions(-) > > diff --git a/sysdeps/x86_64/multiarch/strchr-evex.S b/sysdeps/x86_64/multiarch/strchr-evex.S > index a1c15c4419..c2a0d112f7 100644 > --- a/sysdeps/x86_64/multiarch/strchr-evex.S > +++ b/sysdeps/x86_64/multiarch/strchr-evex.S > @@ -26,48 +26,75 @@ > # define STRCHR __strchr_evex > # endif > > -# define VMOVU vmovdqu64 > -# define VMOVA vmovdqa64 > +# ifndef VEC_SIZE > +# include "x86-evex256-vecs.h" > +# endif > > # ifdef USE_AS_WCSCHR > # define VPBROADCAST vpbroadcastd > -# define VPCMP vpcmpd > +# define VPCMP vpcmpd > +# define VPCMPEQ vpcmpeqd > # define VPTESTN vptestnmd > +# define VPTEST vptestmd > # define VPMINU vpminud > # define CHAR_REG esi > -# define SHIFT_REG ecx > +# define SHIFT_REG rcx > # define CHAR_SIZE 4 > + > +# define USE_WIDE_CHAR > # else > # define VPBROADCAST vpbroadcastb > -# define VPCMP vpcmpb > +# define VPCMP vpcmpb > +# define VPCMPEQ vpcmpeqb > # define VPTESTN vptestnmb > +# define VPTEST vptestmb > # define VPMINU vpminub > # define CHAR_REG sil > -# define SHIFT_REG edx > +# define SHIFT_REG rdi > # define CHAR_SIZE 1 > # endif > > -# define XMMZERO xmm16 > - > -# define YMMZERO ymm16 > -# define YMM0 ymm17 > -# define YMM1 ymm18 > -# define YMM2 ymm19 > -# define YMM3 ymm20 > -# define YMM4 ymm21 > -# define YMM5 ymm22 > -# define YMM6 ymm23 > -# define YMM7 ymm24 > -# define YMM8 ymm25 > - > -# define VEC_SIZE 32 > -# define PAGE_SIZE 4096 > -# define CHAR_PER_VEC (VEC_SIZE / CHAR_SIZE) > - > - .section .text.evex,"ax",@progbits > -ENTRY_P2ALIGN (STRCHR, 5) > - /* Broadcast CHAR to YMM0. */ > - VPBROADCAST %esi, %YMM0 > +# include "reg-macros.h" > + > +# if VEC_SIZE == 64 > +# define MASK_GPR rcx > +# define LOOP_REG rax > + > +# define COND_MASK(k_reg) {%k_reg} > +# else > +# define MASK_GPR rax > +# define LOOP_REG rdi > + > +# define COND_MASK(k_reg) > +# endif > + > +# define CHAR_PER_VEC (VEC_SIZE / CHAR_SIZE) > + > + > +# if CHAR_PER_VEC == 64 > +# define LAST_VEC_OFFSET (VEC_SIZE * 3) > +# define TESTZ(reg) incq %VGPR_SZ(reg, 64) > +# else > + > +# if CHAR_PER_VEC == 32 > +# define TESTZ(reg) incl %VGPR_SZ(reg, 32) > +# elif CHAR_PER_VEC == 16 > +# define TESTZ(reg) incw %VGPR_SZ(reg, 16) > +# else > +# define TESTZ(reg) incb %VGPR_SZ(reg, 8) > +# endif > + > +# define LAST_VEC_OFFSET (VEC_SIZE * 2) > +# endif > + > +# define VMATCH VMM(0) > + > +# define PAGE_SIZE 4096 > + > + .section SECTION(.text), "ax", @progbits > +ENTRY_P2ALIGN (STRCHR, 6) > + /* Broadcast CHAR to VEC_0. */ > + VPBROADCAST %esi, %VMATCH > movl %edi, %eax > andl $(PAGE_SIZE - 1), %eax > /* Check if we cross page boundary with one vector load. > @@ -75,19 +102,27 @@ ENTRY_P2ALIGN (STRCHR, 5) > cmpl $(PAGE_SIZE - VEC_SIZE), %eax > ja L(cross_page_boundary) > > + > /* Check the first VEC_SIZE bytes. Search for both CHAR and the > null bytes. */ > - VMOVU (%rdi), %YMM1 > - > + VMOVU (%rdi), %VMM(1) > /* Leaves only CHARS matching esi as 0. */ > - vpxorq %YMM1, %YMM0, %YMM2 > - VPMINU %YMM2, %YMM1, %YMM2 > - /* Each bit in K0 represents a CHAR or a null byte in YMM1. */ > - VPTESTN %YMM2, %YMM2, %k0 > - kmovd %k0, %eax > - testl %eax, %eax > + vpxorq %VMM(1), %VMATCH, %VMM(2) > + VPMINU %VMM(2), %VMM(1), %VMM(2) > + /* Each bit in K0 represents a CHAR or a null byte in VEC_1. */ > + VPTESTN %VMM(2), %VMM(2), %k0 > + KMOV %k0, %VRAX > +# if VEC_SIZE == 64 && defined USE_AS_STRCHRNUL > + /* If VEC_SIZE == 64 && STRCHRNUL use bsf to test condition so > + that all logic for match/null in first VEC first in 1x cache > + lines. This has a slight cost to larger sizes. */ > + bsf %VRAX, %VRAX > + jz L(aligned_more) > +# else > + test %VRAX, %VRAX > jz L(aligned_more) > - tzcntl %eax, %eax > + bsf %VRAX, %VRAX > +# endif > # ifndef USE_AS_STRCHRNUL > /* Found CHAR or the null byte. */ > cmp (%rdi, %rax, CHAR_SIZE), %CHAR_REG > @@ -109,287 +144,374 @@ ENTRY_P2ALIGN (STRCHR, 5) > # endif > ret > > - > - > - .p2align 4,, 10 > -L(first_vec_x4): > -# ifndef USE_AS_STRCHRNUL > - /* Check to see if first match was CHAR (k0) or null (k1). */ > - kmovd %k0, %eax > - tzcntl %eax, %eax > - kmovd %k1, %ecx > - /* bzhil will not be 0 if first match was null. */ > - bzhil %eax, %ecx, %ecx > - jne L(zero) > -# else > - /* Combine CHAR and null matches. */ > - kord %k0, %k1, %k0 > - kmovd %k0, %eax > - tzcntl %eax, %eax > -# endif > - /* NB: Multiply sizeof char type (1 or 4) to get the number of > - bytes. */ > - leaq (VEC_SIZE * 4)(%rdi, %rax, CHAR_SIZE), %rax > - ret > - > # ifndef USE_AS_STRCHRNUL > L(zero): > xorl %eax, %eax > ret > # endif > > - > - .p2align 4 > + .p2align 4,, 2 > +L(first_vec_x3): > + subq $-(VEC_SIZE * 2), %rdi > +# if VEC_SIZE == 32 > + /* Reuse L(first_vec_x3) for last VEC2 only for VEC_SIZE == 32. > + For VEC_SIZE == 64 the registers don't match. */ > +L(last_vec_x2): > +# endif > L(first_vec_x1): > /* Use bsf here to save 1-byte keeping keeping the block in 1x > fetch block. eax guranteed non-zero. */ > - bsfl %eax, %eax > + bsf %VRCX, %VRCX > # ifndef USE_AS_STRCHRNUL > - /* Found CHAR or the null byte. */ > - cmp (VEC_SIZE)(%rdi, %rax, CHAR_SIZE), %CHAR_REG > + /* Found CHAR or the null byte. */ > + cmp (VEC_SIZE)(%rdi, %rcx, CHAR_SIZE), %CHAR_REG > jne L(zero) > - > # endif > /* NB: Multiply sizeof char type (1 or 4) to get the number of > bytes. */ > - leaq (VEC_SIZE)(%rdi, %rax, CHAR_SIZE), %rax > + leaq (VEC_SIZE)(%rdi, %rcx, CHAR_SIZE), %rax > ret > > - .p2align 4,, 10 > + .p2align 4,, 2 > +L(first_vec_x4): > + subq $-(VEC_SIZE * 2), %rdi > L(first_vec_x2): > # ifndef USE_AS_STRCHRNUL > /* Check to see if first match was CHAR (k0) or null (k1). */ > - kmovd %k0, %eax > - tzcntl %eax, %eax > - kmovd %k1, %ecx > + KMOV %k0, %VRAX > + tzcnt %VRAX, %VRAX > + KMOV %k1, %VRCX > /* bzhil will not be 0 if first match was null. */ > - bzhil %eax, %ecx, %ecx > + bzhi %VRAX, %VRCX, %VRCX > jne L(zero) > # else > /* Combine CHAR and null matches. */ > - kord %k0, %k1, %k0 > - kmovd %k0, %eax > - tzcntl %eax, %eax > + KOR %k0, %k1, %k0 > + KMOV %k0, %VRAX > + bsf %VRAX, %VRAX > # endif > /* NB: Multiply sizeof char type (1 or 4) to get the number of > bytes. */ > leaq (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %rax > ret > > - .p2align 4,, 10 > -L(first_vec_x3): > - /* Use bsf here to save 1-byte keeping keeping the block in 1x > - fetch block. eax guranteed non-zero. */ > - bsfl %eax, %eax > -# ifndef USE_AS_STRCHRNUL > - /* Found CHAR or the null byte. */ > - cmp (VEC_SIZE * 3)(%rdi, %rax, CHAR_SIZE), %CHAR_REG > - jne L(zero) > +# ifdef USE_AS_STRCHRNUL > + /* We use this as a hook to get imm8 encoding for the jmp to > + L(page_cross_boundary). This allows the hot case of a > + match/null-term in first VEC to fit entirely in 1 cache > + line. */ > +L(cross_page_boundary): > + jmp L(cross_page_boundary_real) > # endif > - /* NB: Multiply sizeof char type (1 or 4) to get the number of > - bytes. */ > - leaq (VEC_SIZE * 3)(%rdi, %rax, CHAR_SIZE), %rax > - ret > > .p2align 4 > L(aligned_more): > +L(cross_page_continue): > /* Align data to VEC_SIZE. */ > andq $-VEC_SIZE, %rdi > -L(cross_page_continue): > - /* Check the next 4 * VEC_SIZE. Only one VEC_SIZE at a time since > - data is only aligned to VEC_SIZE. Use two alternating methods > - for checking VEC to balance latency and port contention. */ > > - /* This method has higher latency but has better port > - distribution. */ > - VMOVA (VEC_SIZE)(%rdi), %YMM1 > + /* Check the next 4 * VEC_SIZE. Only one VEC_SIZE at a time > + since data is only aligned to VEC_SIZE. Use two alternating > + methods for checking VEC to balance latency and port > + contention. */ > + > + /* Method(1) with 8c latency: > + For VEC_SIZE == 32: > + p0 * 1.83, p1 * 0.83, p5 * 1.33 > + For VEC_SIZE == 64: > + p0 * 2.50, p1 * 0.00, p5 * 1.50 */ > + VMOVA (VEC_SIZE)(%rdi), %VMM(1) > /* Leaves only CHARS matching esi as 0. */ > - vpxorq %YMM1, %YMM0, %YMM2 > - VPMINU %YMM2, %YMM1, %YMM2 > - /* Each bit in K0 represents a CHAR or a null byte in YMM1. */ > - VPTESTN %YMM2, %YMM2, %k0 > - kmovd %k0, %eax > - testl %eax, %eax > + vpxorq %VMM(1), %VMATCH, %VMM(2) > + VPMINU %VMM(2), %VMM(1), %VMM(2) > + /* Each bit in K0 represents a CHAR or a null byte in VEC_1. */ > + VPTESTN %VMM(2), %VMM(2), %k0 > + KMOV %k0, %VRCX > + test %VRCX, %VRCX > jnz L(first_vec_x1) > > - /* This method has higher latency but has better port > - distribution. */ > - VMOVA (VEC_SIZE * 2)(%rdi), %YMM1 > - /* Each bit in K0 represents a CHAR in YMM1. */ > - VPCMP $0, %YMM1, %YMM0, %k0 > - /* Each bit in K1 represents a CHAR in YMM1. */ > - VPTESTN %YMM1, %YMM1, %k1 > - kortestd %k0, %k1 > + /* Method(2) with 6c latency: > + For VEC_SIZE == 32: > + p0 * 1.00, p1 * 0.00, p5 * 2.00 > + For VEC_SIZE == 64: > + p0 * 1.00, p1 * 0.00, p5 * 2.00 */ > + VMOVA (VEC_SIZE * 2)(%rdi), %VMM(1) > + /* Each bit in K0 represents a CHAR in VEC_1. */ > + VPCMPEQ %VMM(1), %VMATCH, %k0 > + /* Each bit in K1 represents a CHAR in VEC_1. */ > + VPTESTN %VMM(1), %VMM(1), %k1 > + KORTEST %k0, %k1 > jnz L(first_vec_x2) > > - VMOVA (VEC_SIZE * 3)(%rdi), %YMM1 > + /* By swapping between Method 1/2 we get more fair port > + distrubition and better throughput. */ > + > + VMOVA (VEC_SIZE * 3)(%rdi), %VMM(1) > /* Leaves only CHARS matching esi as 0. */ > - vpxorq %YMM1, %YMM0, %YMM2 > - VPMINU %YMM2, %YMM1, %YMM2 > - /* Each bit in K0 represents a CHAR or a null byte in YMM1. */ > - VPTESTN %YMM2, %YMM2, %k0 > - kmovd %k0, %eax > - testl %eax, %eax > + vpxorq %VMM(1), %VMATCH, %VMM(2) > + VPMINU %VMM(2), %VMM(1), %VMM(2) > + /* Each bit in K0 represents a CHAR or a null byte in VEC_1. */ > + VPTESTN %VMM(2), %VMM(2), %k0 > + KMOV %k0, %VRCX > + test %VRCX, %VRCX > jnz L(first_vec_x3) > > - VMOVA (VEC_SIZE * 4)(%rdi), %YMM1 > - /* Each bit in K0 represents a CHAR in YMM1. */ > - VPCMP $0, %YMM1, %YMM0, %k0 > - /* Each bit in K1 represents a CHAR in YMM1. */ > - VPTESTN %YMM1, %YMM1, %k1 > - kortestd %k0, %k1 > + VMOVA (VEC_SIZE * 4)(%rdi), %VMM(1) > + /* Each bit in K0 represents a CHAR in VEC_1. */ > + VPCMPEQ %VMM(1), %VMATCH, %k0 > + /* Each bit in K1 represents a CHAR in VEC_1. */ > + VPTESTN %VMM(1), %VMM(1), %k1 > + KORTEST %k0, %k1 > jnz L(first_vec_x4) > > /* Align data to VEC_SIZE * 4 for the loop. */ > +# if VEC_SIZE == 64 > + /* Use rax for the loop reg as it allows to the loop to fit in > + exactly 2-cache-lines. (more efficient imm32 + gpr > + encoding). */ > + leaq (VEC_SIZE)(%rdi), %rax > + /* No partial register stalls on evex512 processors. */ > + xorb %al, %al > +# else > + /* For VEC_SIZE == 32 continue using rdi for loop reg so we can > + reuse more code and save space. */ > addq $VEC_SIZE, %rdi > andq $-(VEC_SIZE * 4), %rdi > - > +# endif > .p2align 4 > L(loop_4x_vec): > - /* Check 4x VEC at a time. No penalty to imm32 offset with evex > - encoding. */ > - VMOVA (VEC_SIZE * 4)(%rdi), %YMM1 > - VMOVA (VEC_SIZE * 5)(%rdi), %YMM2 > - VMOVA (VEC_SIZE * 6)(%rdi), %YMM3 > - VMOVA (VEC_SIZE * 7)(%rdi), %YMM4 > - > - /* For YMM1 and YMM3 use xor to set the CHARs matching esi to > + /* Check 4x VEC at a time. No penalty for imm32 offset with evex > + encoding (if offset % VEC_SIZE == 0). */ > + VMOVA (VEC_SIZE * 4)(%LOOP_REG), %VMM(1) > + VMOVA (VEC_SIZE * 5)(%LOOP_REG), %VMM(2) > + VMOVA (VEC_SIZE * 6)(%LOOP_REG), %VMM(3) > + VMOVA (VEC_SIZE * 7)(%LOOP_REG), %VMM(4) > + > + /* Collect bits where VEC_1 does NOT match esi. This is later > + use to mask of results (getting not matches allows us to > + save an instruction on combining). */ > + VPCMP $4, %VMATCH, %VMM(1), %k1 > + > + /* Two methods for loop depending on VEC_SIZE. This is because > + with zmm registers VPMINU can only run on p0 (as opposed to > + p0/p1 for ymm) so it is less prefered. */ > +# if VEC_SIZE == 32 > + /* For VEC_2 and VEC_3 use xor to set the CHARs matching esi to > zero. */ > - vpxorq %YMM1, %YMM0, %YMM5 > - /* For YMM2 and YMM4 cmp not equals to CHAR and store result in > - k register. Its possible to save either 1 or 2 instructions > - using cmp no equals method for either YMM1 or YMM1 and YMM3 > - respectively but bottleneck on p5 makes it not worth it. */ > - VPCMP $4, %YMM0, %YMM2, %k2 > - vpxorq %YMM3, %YMM0, %YMM7 > - VPCMP $4, %YMM0, %YMM4, %k4 > - > - /* Use min to select all zeros from either xor or end of string). > - */ > - VPMINU %YMM1, %YMM5, %YMM1 > - VPMINU %YMM3, %YMM7, %YMM3 > + vpxorq %VMM(2), %VMATCH, %VMM(6) > + vpxorq %VMM(3), %VMATCH, %VMM(7) > > - /* Use min + zeromask to select for zeros. Since k2 and k4 will > - have 0 as positions that matched with CHAR which will set > - zero in the corresponding destination bytes in YMM2 / YMM4. > - */ > - VPMINU %YMM1, %YMM2, %YMM2{%k2}{z} > - VPMINU %YMM3, %YMM4, %YMM4 > - VPMINU %YMM2, %YMM4, %YMM4{%k4}{z} > - > - VPTESTN %YMM4, %YMM4, %k1 > - kmovd %k1, %ecx > - subq $-(VEC_SIZE * 4), %rdi > - testl %ecx, %ecx > + /* Find non-matches in VEC_4 while combining with non-matches > + from VEC_1. NB: Try and use masked predicate execution on > + instructions that have mask result as it has no latency > + penalty. */ > + VPCMP $4, %VMATCH, %VMM(4), %k4{%k1} > + > + /* Combined zeros from VEC_1 / VEC_2 (search for null term). */ > + VPMINU %VMM(1), %VMM(2), %VMM(2) > + > + /* Use min to select all zeros from either xor or end of > + string). */ > + VPMINU %VMM(3), %VMM(7), %VMM(3) > + VPMINU %VMM(2), %VMM(6), %VMM(2) > + > + /* Combined zeros from VEC_2 / VEC_3 (search for null term). */ > + VPMINU %VMM(3), %VMM(4), %VMM(4) > + > + /* Combined zeros from VEC_2 / VEC_4 (this has all null term and > + esi matches for VEC_2 / VEC_3). */ > + VPMINU %VMM(2), %VMM(4), %VMM(4) > +# else > + /* Collect non-matches for VEC_2. */ > + VPCMP $4, %VMM(2), %VMATCH, %k2 > + > + /* Combined zeros from VEC_1 / VEC_2 (search for null term). */ > + VPMINU %VMM(1), %VMM(2), %VMM(2) > + > + /* Find non-matches in VEC_3/VEC_4 while combining with non- > + matches from VEC_1/VEC_2 respectively. */ > + VPCMP $4, %VMM(3), %VMATCH, %k3{%k1} > + VPCMP $4, %VMM(4), %VMATCH, %k4{%k2} > + > + /* Finish combining zeros in all VECs. */ > + VPMINU %VMM(3), %VMM(4), %VMM(4) > + > + /* Combine in esi matches for VEC_3 (if there was a match with > + esi, the corresponding bit in %k3 is zero so the > + VPMINU_MASKZ will have a zero in the result). NB: This make > + the VPMINU 3c latency. The only way to avoid it is to > + createa a 12c dependency chain on all the `VPCMP $4, ...` > + which has higher total latency. */ > + VPMINU %VMM(2), %VMM(4), %VMM(4){%k3}{z} > +# endif > + VPTEST %VMM(4), %VMM(4), %k0{%k4} > + KMOV %k0, %VRDX > + subq $-(VEC_SIZE * 4), %LOOP_REG > + > + /* TESTZ is inc using the proper register width depending on > + CHAR_PER_VEC. An esi match or null-term match leaves a zero- > + bit in rdx so inc won't overflow and won't be zero. */ > + TESTZ (rdx) > jz L(loop_4x_vec) > > - VPTESTN %YMM1, %YMM1, %k0 > - kmovd %k0, %eax > - testl %eax, %eax > - jnz L(last_vec_x1) > + VPTEST %VMM(1), %VMM(1), %k0{%k1} > + KMOV %k0, %VGPR(MASK_GPR) > + TESTZ (MASK_GPR) > +# if VEC_SIZE == 32 > + /* We can reuse the return code in page_cross logic for VEC_SIZE > + == 32. */ > + jnz L(last_vec_x1_vec_size32) > +# else > + jnz L(last_vec_x1_vec_size64) > +# endif > + > > - VPTESTN %YMM2, %YMM2, %k0 > - kmovd %k0, %eax > - testl %eax, %eax > + /* COND_MASK integates the esi matches for VEC_SIZE == 64. For > + VEC_SIZE == 32 they are already integrated. */ > + VPTEST %VMM(2), %VMM(2), %k0 COND_MASK(k2) > + KMOV %k0, %VRCX > + TESTZ (rcx) > jnz L(last_vec_x2) > > - VPTESTN %YMM3, %YMM3, %k0 > - kmovd %k0, %eax > - /* Combine YMM3 matches (eax) with YMM4 matches (ecx). */ > -# ifdef USE_AS_WCSCHR > - sall $8, %ecx > - orl %ecx, %eax > - bsfl %eax, %eax > + VPTEST %VMM(3), %VMM(3), %k0 COND_MASK(k3) > + KMOV %k0, %VRCX > +# if CHAR_PER_VEC == 64 > + TESTZ (rcx) > + jnz L(last_vec_x3) > # else > - salq $32, %rcx > - orq %rcx, %rax > - bsfq %rax, %rax > + salq $CHAR_PER_VEC, %rdx > + TESTZ (rcx) > + orq %rcx, %rdx > # endif > + > + bsfq %rdx, %rdx > + > # ifndef USE_AS_STRCHRNUL > /* Check if match was CHAR or null. */ > - cmp (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %CHAR_REG > + cmp (LAST_VEC_OFFSET)(%LOOP_REG, %rdx, CHAR_SIZE), %CHAR_REG > jne L(zero_end) > # endif > /* NB: Multiply sizeof char type (1 or 4) to get the number of > bytes. */ > - leaq (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %rax > + leaq (LAST_VEC_OFFSET)(%LOOP_REG, %rdx, CHAR_SIZE), %rax > ret > > - .p2align 4,, 8 > -L(last_vec_x1): > - bsfl %eax, %eax > -# ifdef USE_AS_WCSCHR > - /* NB: Multiply wchar_t count by 4 to get the number of bytes. > - */ > - leaq (%rdi, %rax, CHAR_SIZE), %rax > -# else > - addq %rdi, %rax > +# ifndef USE_AS_STRCHRNUL > +L(zero_end): > + xorl %eax, %eax > + ret > # endif > > -# ifndef USE_AS_STRCHRNUL > + > + /* Seperate return label for last VEC1 because for VEC_SIZE == > + 32 we can reuse return code in L(page_cross) but VEC_SIZE == > + 64 has mismatched registers. */ > +# if VEC_SIZE == 64 > + .p2align 4,, 8 > +L(last_vec_x1_vec_size64): > + bsf %VRCX, %VRCX > +# ifndef USE_AS_STRCHRNUL > /* Check if match was null. */ > - cmp (%rax), %CHAR_REG > + cmp (%rax, %rcx, CHAR_SIZE), %CHAR_REG > jne L(zero_end) > -# endif > - > +# endif > +# ifdef USE_AS_WCSCHR > + /* NB: Multiply wchar_t count by 4 to get the number of bytes. > + */ > + leaq (%rax, %rcx, CHAR_SIZE), %rax > +# else > + addq %rcx, %rax > +# endif > ret > > + /* Since we can't combine the last 2x matches for CHAR_PER_VEC > + == 64 we need return label for last VEC3. */ > +# if CHAR_PER_VEC == 64 > .p2align 4,, 8 > +L(last_vec_x3): > + addq $VEC_SIZE, %LOOP_REG > +# endif > + > + /* Duplicate L(last_vec_x2) for VEC_SIZE == 64 because we can't > + reuse L(first_vec_x3) due to register mismatch. */ > L(last_vec_x2): > - bsfl %eax, %eax > -# ifndef USE_AS_STRCHRNUL > + bsf %VGPR(MASK_GPR), %VGPR(MASK_GPR) > +# ifndef USE_AS_STRCHRNUL > /* Check if match was null. */ > - cmp (VEC_SIZE)(%rdi, %rax, CHAR_SIZE), %CHAR_REG > + cmp (VEC_SIZE * 1)(%LOOP_REG, %MASK_GPR, CHAR_SIZE), %CHAR_REG > jne L(zero_end) > -# endif > +# endif > /* NB: Multiply sizeof char type (1 or 4) to get the number of > bytes. */ > - leaq (VEC_SIZE)(%rdi, %rax, CHAR_SIZE), %rax > + leaq (VEC_SIZE * 1)(%LOOP_REG, %MASK_GPR, CHAR_SIZE), %rax > ret > +# endif > > - /* Cold case for crossing page with first load. */ > - .p2align 4,, 8 > + /* Cold case for crossing page with first load. */ > + .p2align 4,, 10 > +# ifndef USE_AS_STRCHRNUL > L(cross_page_boundary): > - movq %rdi, %rdx > +# endif > +L(cross_page_boundary_real): > /* Align rdi. */ > - andq $-VEC_SIZE, %rdi > - VMOVA (%rdi), %YMM1 > - /* Leaves only CHARS matching esi as 0. */ > - vpxorq %YMM1, %YMM0, %YMM2 > - VPMINU %YMM2, %YMM1, %YMM2 > - /* Each bit in K0 represents a CHAR or a null byte in YMM1. */ > - VPTESTN %YMM2, %YMM2, %k0 > - kmovd %k0, %eax > + xorq %rdi, %rax > + VMOVA (PAGE_SIZE - VEC_SIZE)(%rax), %VMM(1) > + /* Use high latency method of getting matches to save code size. > + */ > + > + /* K1 has 1s where VEC(1) does NOT match esi. */ > + VPCMP $4, %VMM(1), %VMATCH, %k1 > + /* K0 has ones where K1 is 1 (non-match with esi), and non-zero > + (null). */ > + VPTEST %VMM(1), %VMM(1), %k0{%k1} > + KMOV %k0, %VRAX > /* Remove the leading bits. */ > # ifdef USE_AS_WCSCHR > - movl %edx, %SHIFT_REG > + movl %edi, %VGPR_SZ(SHIFT_REG, 32) > /* NB: Divide shift count by 4 since each bit in K1 represent 4 > bytes. */ > - sarl $2, %SHIFT_REG > - andl $(CHAR_PER_VEC - 1), %SHIFT_REG > + sarl $2, %VGPR_SZ(SHIFT_REG, 32) > + andl $(CHAR_PER_VEC - 1), %VGPR_SZ(SHIFT_REG, 32) > + > + /* if wcsrchr we need to reverse matches as we can't rely on > + signed shift to bring in ones. There is not sarx for > + gpr8/16. Also not we can't use inc here as the lower bits > + represent matches out of range so we can't rely on overflow. > + */ > + xorl $((1 << CHAR_PER_VEC)- 1), %eax > +# endif > + /* Use arithmatic shift so that leading 1s are filled in. */ > + sarx %VGPR(SHIFT_REG), %VRAX, %VRAX > + /* If eax is all ones then no matches for esi or NULL. */ > + > +# ifdef USE_AS_WCSCHR > + test %VRAX, %VRAX > +# else > + inc %VRAX > # endif > - sarxl %SHIFT_REG, %eax, %eax > - /* If eax is zero continue. */ > - testl %eax, %eax > jz L(cross_page_continue) > - bsfl %eax, %eax > > + .p2align 4,, 10 > +L(last_vec_x1_vec_size32): > + bsf %VRAX, %VRAX > # ifdef USE_AS_WCSCHR > - /* NB: Multiply wchar_t count by 4 to get the number of > - bytes. */ > - leaq (%rdx, %rax, CHAR_SIZE), %rax > + /* NB: Multiply wchar_t count by 4 to get the number of bytes. > + */ > + leaq (%rdi, %rax, CHAR_SIZE), %rax > # else > - addq %rdx, %rax > + addq %rdi, %rax > # endif > # ifndef USE_AS_STRCHRNUL > /* Check to see if match was CHAR or null. */ > cmp (%rax), %CHAR_REG > - je L(cross_page_ret) > -L(zero_end): > - xorl %eax, %eax > -L(cross_page_ret): > + jne L(zero_end_0) > # endif > ret > +# ifndef USE_AS_STRCHRNUL > +L(zero_end_0): > + xorl %eax, %eax > + ret > +# endif > > END (STRCHR) > #endif > -- > 2.34.1 > Results For: strchr alignment,length ,max_char ,pos ,rand ,seek_char ,__strchr_evex ,__strchr_evex_orig 0 ,1 ,127 ,0 ,0 ,0 ,3.484 ,3.482 ,1.001 0 ,1 ,127 ,0 ,0 ,23 ,3.549 ,3.577 ,0.992 0 ,10 ,127 ,9 ,0 ,0 ,3.764 ,3.774 ,0.997 0 ,10 ,127 ,9 ,0 ,23 ,3.667 ,3.725 ,0.985 0 ,1024 ,127 ,1056 ,0 ,0 ,29.009 ,29.496 ,0.983 0 ,1024 ,127 ,1088 ,0 ,0 ,30.558 ,29.533 ,1.035 0 ,1024 ,127 ,1120 ,0 ,0 ,28.984 ,29.538 ,0.981 0 ,1024 ,127 ,1152 ,0 ,0 ,29.12 ,29.453 ,0.989 0 ,1024 ,127 ,1184 ,0 ,0 ,28.992 ,29.719 ,0.976 0 ,1024 ,127 ,1216 ,0 ,0 ,29.231 ,29.728 ,0.983 0 ,1024 ,127 ,1248 ,0 ,0 ,28.974 ,29.482 ,0.983 0 ,1024 ,127 ,1280 ,0 ,0 ,30.446 ,31.0 ,0.982 0 ,1024 ,127 ,1312 ,0 ,0 ,28.923 ,29.424 ,0.983 0 ,1024 ,127 ,1344 ,0 ,0 ,29.066 ,29.51 ,0.985 0 ,1024 ,127 ,704 ,0 ,0 ,23.787 ,24.111 ,0.987 0 ,1024 ,127 ,736 ,0 ,0 ,24.089 ,23.965 ,1.005 0 ,1024 ,127 ,768 ,0 ,0 ,23.96 ,24.187 ,0.991 0 ,1024 ,127 ,800 ,0 ,0 ,24.756 ,25.882 ,0.957 0 ,1024 ,127 ,832 ,0 ,0 ,27.218 ,27.062 ,1.006 0 ,1024 ,127 ,864 ,0 ,0 ,26.651 ,27.02 ,0.986 0 ,1024 ,127 ,896 ,0 ,0 ,26.368 ,26.469 ,0.996 0 ,1024 ,127 ,928 ,0 ,0 ,27.253 ,28.029 ,0.972 0 ,1024 ,127 ,960 ,0 ,0 ,28.766 ,29.732 ,0.968 0 ,1024 ,127 ,992 ,0 ,0 ,29.113 ,29.589 ,0.984 0 ,1056 ,127 ,1024 ,0 ,0 ,29.376 ,29.74 ,0.988 0 ,1088 ,127 ,1024 ,0 ,0 ,28.924 ,29.572 ,0.978 0 ,11 ,127 ,10 ,0 ,0 ,3.801 ,3.762 ,1.01 0 ,11 ,127 ,10 ,0 ,23 ,3.867 ,3.724 ,1.038 0 ,112 ,127 ,16 ,0 ,0 ,3.581 ,3.788 ,0.945 0 ,1120 ,127 ,1024 ,0 ,0 ,28.917 ,29.617 ,0.976 0 ,1152 ,127 ,1024 ,0 ,0 ,29.024 ,29.636 ,0.979 0 ,1184 ,127 ,1024 ,0 ,0 ,29.117 ,29.367 ,0.991 0 ,12 ,127 ,11 ,0 ,0 ,3.749 ,3.813 ,0.983 0 ,12 ,127 ,11 ,0 ,23 ,3.85 ,3.75 ,1.027 0 ,1216 ,127 ,1024 ,0 ,0 ,32.235 ,32.195 ,1.001 0 ,1248 ,127 ,1024 ,0 ,0 ,29.111 ,29.558 ,0.985 0 ,128 ,127 ,160 ,0 ,0 ,7.904 ,8.004 ,0.988 0 ,128 ,127 ,192 ,0 ,0 ,7.678 ,8.022 ,0.957 0 ,128 ,127 ,224 ,0 ,0 ,7.665 ,7.954 ,0.964 0 ,128 ,127 ,256 ,0 ,0 ,7.697 ,7.944 ,0.969 0 ,128 ,127 ,288 ,0 ,0 ,7.658 ,7.986 ,0.959 0 ,128 ,127 ,32 ,0 ,0 ,4.469 ,5.122 ,0.873 0 ,128 ,127 ,320 ,0 ,0 ,7.617 ,7.951 ,0.958 0 ,128 ,127 ,352 ,0 ,0 ,7.67 ,7.933 ,0.967 0 ,128 ,127 ,384 ,0 ,0 ,7.67 ,7.962 ,0.963 0 ,128 ,127 ,416 ,0 ,0 ,7.642 ,7.925 ,0.964 0 ,128 ,127 ,448 ,0 ,0 ,7.694 ,8.028 ,0.958 0 ,128 ,127 ,64 ,0 ,0 ,5.725 ,6.131 ,0.934 0 ,128 ,127 ,96 ,0 ,0 ,6.267 ,6.434 ,0.974 0 ,1280 ,127 ,1024 ,0 ,0 ,28.901 ,29.648 ,0.975 0 ,13 ,127 ,12 ,0 ,0 ,3.878 ,3.87 ,1.002 0 ,13 ,127 ,12 ,0 ,23 ,3.908 ,3.798 ,1.029 0 ,1312 ,127 ,1024 ,0 ,0 ,29.025 ,29.584 ,0.981 0 ,1344 ,127 ,1024 ,0 ,0 ,29.021 ,29.673 ,0.978 0 ,14 ,127 ,13 ,0 ,0 ,3.717 ,3.81 ,0.976 0 ,14 ,127 ,13 ,0 ,23 ,3.882 ,3.824 ,1.015 0 ,144 ,127 ,16 ,0 ,0 ,3.672 ,3.791 ,0.968 0 ,15 ,127 ,14 ,0 ,0 ,3.635 ,3.822 ,0.951 0 ,15 ,127 ,14 ,0 ,23 ,3.923 ,3.944 ,0.995 0 ,16 ,127 ,112 ,0 ,0 ,3.77 ,3.777 ,0.998 0 ,16 ,127 ,144 ,0 ,0 ,3.639 ,3.777 ,0.963 0 ,16 ,127 ,15 ,0 ,0 ,3.757 ,3.882 ,0.968 0 ,16 ,127 ,15 ,0 ,23 ,3.785 ,3.842 ,0.985 0 ,16 ,127 ,176 ,0 ,0 ,3.624 ,3.797 ,0.954 0 ,16 ,127 ,208 ,0 ,0 ,3.773 ,3.785 ,0.997 0 ,16 ,127 ,240 ,0 ,0 ,3.705 ,3.8 ,0.975 0 ,16 ,127 ,272 ,0 ,0 ,3.679 ,3.693 ,0.996 0 ,16 ,127 ,304 ,0 ,0 ,3.651 ,3.87 ,0.943 0 ,16 ,127 ,336 ,0 ,0 ,3.882 ,3.79 ,1.024 0 ,16 ,127 ,48 ,0 ,0 ,3.59 ,3.675 ,0.977 0 ,16 ,127 ,80 ,0 ,0 ,3.705 ,3.756 ,0.986 0 ,160 ,127 ,128 ,0 ,0 ,7.638 ,7.97 ,0.958 0 ,160 ,127 ,256 ,0 ,0 ,11.478 ,11.872 ,0.967 0 ,160 ,127 ,32 ,0 ,0 ,4.484 ,5.186 ,0.865 0 ,160 ,127 ,64 ,0 ,0 ,5.722 ,6.116 ,0.936 0 ,17 ,127 ,16 ,0 ,0 ,3.78 ,3.857 ,0.98 0 ,17 ,127 ,16 ,0 ,23 ,3.808 ,3.803 ,1.001 0 ,1728 ,127 ,2048 ,0 ,0 ,44.094 ,44.594 ,0.989 0 ,176 ,127 ,16 ,0 ,0 ,3.691 ,3.774 ,0.978 0 ,1760 ,127 ,2048 ,0 ,0 ,44.531 ,44.645 ,0.997 0 ,1792 ,127 ,2048 ,0 ,0 ,44.158 ,44.741 ,0.987 0 ,18 ,127 ,17 ,0 ,0 ,3.749 ,3.829 ,0.979 0 ,18 ,127 ,17 ,0 ,23 ,3.763 ,3.821 ,0.985 0 ,1824 ,127 ,2048 ,0 ,0 ,45.962 ,47.852 ,0.961 0 ,1856 ,127 ,2048 ,0 ,0 ,46.911 ,46.994 ,0.998 0 ,1888 ,127 ,2048 ,0 ,0 ,46.859 ,47.08 ,0.995 0 ,19 ,127 ,18 ,0 ,0 ,3.794 ,3.774 ,1.005 0 ,19 ,127 ,18 ,0 ,23 ,3.716 ,3.831 ,0.97 0 ,192 ,127 ,128 ,0 ,0 ,7.664 ,8.001 ,0.958 0 ,192 ,127 ,256 ,0 ,0 ,13.449 ,13.331 ,1.009 0 ,192 ,127 ,32 ,0 ,0 ,4.61 ,5.183 ,0.889 0 ,192 ,127 ,512 ,0 ,0 ,12.659 ,13.106 ,0.966 0 ,192 ,127 ,64 ,0 ,0 ,5.733 ,6.114 ,0.938 0 ,1920 ,127 ,2048 ,0 ,0 ,46.512 ,46.564 ,0.999 0 ,1952 ,127 ,2048 ,0 ,0 ,47.817 ,48.691 ,0.982 0 ,1984 ,127 ,2048 ,0 ,0 ,49.355 ,50.161 ,0.984 0 ,2 ,127 ,1 ,0 ,0 ,3.699 ,3.743 ,0.988 0 ,2 ,127 ,1 ,0 ,23 ,3.697 ,3.704 ,0.998 0 ,20 ,127 ,19 ,0 ,0 ,3.717 ,3.758 ,0.989 0 ,20 ,127 ,19 ,0 ,23 ,3.662 ,3.829 ,0.956 0 ,2016 ,127 ,2048 ,0 ,0 ,49.752 ,49.795 ,0.999 0 ,2048 ,127 ,1024 ,0 ,0 ,31.515 ,30.241 ,1.042 0 ,2048 ,127 ,1024 ,0 ,23 ,29.306 ,30.083 ,0.974 0 ,2048 ,127 ,128 ,0 ,0 ,7.675 ,8.03 ,0.956 0 ,2048 ,127 ,128 ,0 ,23 ,7.827 ,7.93 ,0.987 0 ,2048 ,127 ,1728 ,0 ,0 ,44.263 ,44.614 ,0.992 0 ,2048 ,127 ,1760 ,0 ,0 ,44.122 ,44.538 ,0.991 0 ,2048 ,127 ,1792 ,0 ,0 ,44.0 ,44.677 ,0.985 0 ,2048 ,127 ,1824 ,0 ,0 ,45.275 ,46.338 ,0.977 0 ,2048 ,127 ,1856 ,0 ,0 ,46.763 ,47.028 ,0.994 0 ,2048 ,127 ,1888 ,0 ,0 ,46.854 ,47.025 ,0.996 0 ,2048 ,127 ,1920 ,0 ,0 ,46.518 ,46.679 ,0.997 0 ,2048 ,127 ,1952 ,0 ,0 ,47.9 ,48.726 ,0.983 0 ,2048 ,127 ,1984 ,0 ,0 ,49.596 ,49.835 ,0.995 0 ,2048 ,127 ,2016 ,0 ,0 ,49.767 ,49.671 ,1.002 0 ,2048 ,127 ,2048 ,0 ,0 ,49.438 ,49.743 ,0.994 0 ,2048 ,127 ,2048 ,0 ,23 ,49.619 ,51.643 ,0.961 0 ,2048 ,127 ,2080 ,0 ,0 ,49.35 ,49.306 ,1.001 0 ,2048 ,127 ,2112 ,0 ,0 ,49.517 ,49.302 ,1.004 0 ,2048 ,127 ,2144 ,0 ,0 ,49.677 ,49.31 ,1.007 0 ,2048 ,127 ,2176 ,0 ,0 ,51.055 ,49.334 ,1.035 0 ,2048 ,127 ,2208 ,0 ,0 ,48.811 ,49.293 ,0.99 0 ,2048 ,127 ,2240 ,0 ,0 ,49.336 ,49.366 ,0.999 0 ,2048 ,127 ,2272 ,0 ,0 ,49.354 ,49.432 ,0.998 0 ,2048 ,127 ,2304 ,0 ,0 ,49.361 ,49.314 ,1.001 0 ,2048 ,127 ,2336 ,0 ,0 ,50.948 ,49.404 ,1.031 0 ,2048 ,127 ,2368 ,0 ,0 ,49.49 ,49.145 ,1.007 0 ,2048 ,127 ,256 ,0 ,0 ,13.201 ,13.373 ,0.987 0 ,2048 ,127 ,256 ,0 ,23 ,13.305 ,13.412 ,0.992 0 ,2048 ,127 ,32 ,0 ,0 ,4.417 ,5.272 ,0.838 0 ,2048 ,127 ,32 ,0 ,23 ,4.279 ,4.939 ,0.866 0 ,2048 ,127 ,512 ,0 ,0 ,19.755 ,20.248 ,0.976 0 ,2048 ,127 ,512 ,0 ,23 ,19.304 ,19.867 ,0.972 0 ,2048 ,127 ,64 ,0 ,0 ,5.777 ,6.178 ,0.935 0 ,2048 ,127 ,64 ,0 ,23 ,5.782 ,6.039 ,0.957 0 ,208 ,127 ,16 ,0 ,0 ,3.842 ,3.815 ,1.007 0 ,2080 ,127 ,2048 ,0 ,0 ,50.755 ,49.293 ,1.03 0 ,21 ,127 ,20 ,0 ,0 ,3.639 ,3.785 ,0.961 0 ,21 ,127 ,20 ,0 ,23 ,3.782 ,3.783 ,1.0 0 ,2112 ,127 ,2048 ,0 ,0 ,49.595 ,49.264 ,1.007 0 ,2144 ,127 ,2048 ,0 ,0 ,48.922 ,49.41 ,0.99 0 ,2176 ,127 ,2048 ,0 ,0 ,49.269 ,49.334 ,0.999 0 ,22 ,127 ,21 ,0 ,0 ,3.809 ,3.81 ,1.0 0 ,22 ,127 ,21 ,0 ,23 ,3.766 ,3.815 ,0.987 0 ,2208 ,127 ,2048 ,0 ,0 ,49.252 ,49.21 ,1.001 0 ,224 ,127 ,128 ,0 ,0 ,7.663 ,8.045 ,0.952 0 ,224 ,127 ,256 ,0 ,0 ,12.533 ,13.126 ,0.955 0 ,224 ,127 ,32 ,0 ,0 ,4.526 ,5.154 ,0.878 0 ,224 ,127 ,512 ,0 ,0 ,12.546 ,13.085 ,0.959 0 ,224 ,127 ,64 ,0 ,0 ,5.732 ,6.097 ,0.94 0 ,2240 ,127 ,2048 ,0 ,0 ,49.802 ,49.194 ,1.012 0 ,2272 ,127 ,2048 ,0 ,0 ,49.469 ,49.332 ,1.003 0 ,23 ,127 ,22 ,0 ,0 ,3.958 ,3.873 ,1.022 0 ,23 ,127 ,22 ,0 ,23 ,3.796 ,3.838 ,0.989 0 ,2304 ,127 ,2048 ,0 ,0 ,49.215 ,49.287 ,0.999 0 ,2336 ,127 ,2048 ,0 ,0 ,49.271 ,49.267 ,1.0 0 ,2368 ,127 ,2048 ,0 ,0 ,49.236 ,49.279 ,0.999 0 ,24 ,127 ,23 ,0 ,0 ,3.646 ,3.808 ,0.958 0 ,24 ,127 ,23 ,0 ,23 ,3.839 ,3.779 ,1.016 0 ,240 ,127 ,16 ,0 ,0 ,3.768 ,3.827 ,0.984 0 ,25 ,127 ,24 ,0 ,0 ,3.785 ,3.813 ,0.993 0 ,25 ,127 ,24 ,0 ,23 ,3.853 ,3.838 ,1.004 0 ,256 ,127 ,128 ,0 ,0 ,7.66 ,7.949 ,0.964 0 ,256 ,127 ,160 ,0 ,0 ,12.312 ,12.208 ,1.009 0 ,256 ,127 ,192 ,0 ,0 ,12.436 ,13.071 ,0.951 0 ,256 ,127 ,224 ,0 ,0 ,12.381 ,13.039 ,0.949 0 ,256 ,127 ,288 ,0 ,0 ,13.236 ,13.383 ,0.989 0 ,256 ,127 ,32 ,0 ,0 ,4.482 ,5.181 ,0.865 0 ,256 ,127 ,320 ,0 ,0 ,13.176 ,13.428 ,0.981 0 ,256 ,127 ,352 ,0 ,0 ,13.174 ,13.41 ,0.982 0 ,256 ,127 ,384 ,0 ,0 ,13.2 ,13.363 ,0.988 0 ,256 ,127 ,416 ,0 ,0 ,13.196 ,13.39 ,0.985 0 ,256 ,127 ,448 ,0 ,0 ,13.205 ,13.356 ,0.989 0 ,256 ,127 ,480 ,0 ,0 ,13.28 ,13.438 ,0.988 0 ,256 ,127 ,512 ,0 ,0 ,13.222 ,13.408 ,0.986 0 ,256 ,127 ,544 ,0 ,0 ,13.202 ,13.366 ,0.988 0 ,256 ,127 ,576 ,0 ,0 ,13.238 ,13.423 ,0.986 0 ,256 ,127 ,64 ,0 ,0 ,5.76 ,6.152 ,0.936 0 ,256 ,127 ,96 ,0 ,0 ,6.315 ,6.431 ,0.982 0 ,26 ,127 ,25 ,0 ,0 ,3.771 ,3.751 ,1.005 0 ,26 ,127 ,25 ,0 ,23 ,3.723 ,3.83 ,0.972 0 ,27 ,127 ,26 ,0 ,0 ,3.72 ,3.799 ,0.979 0 ,27 ,127 ,26 ,0 ,23 ,3.613 ,3.727 ,0.969 0 ,272 ,127 ,16 ,0 ,0 ,3.8 ,3.681 ,1.032 0 ,28 ,127 ,27 ,0 ,0 ,3.77 ,3.881 ,0.972 0 ,28 ,127 ,27 ,0 ,23 ,3.767 ,3.77 ,0.999 0 ,288 ,127 ,128 ,0 ,0 ,7.678 ,7.993 ,0.96 0 ,288 ,127 ,256 ,0 ,0 ,13.302 ,13.406 ,0.992 0 ,288 ,127 ,32 ,0 ,0 ,4.601 ,5.171 ,0.89 0 ,288 ,127 ,512 ,0 ,0 ,14.188 ,14.563 ,0.974 0 ,288 ,127 ,64 ,0 ,0 ,5.692 ,6.088 ,0.935 0 ,29 ,127 ,28 ,0 ,0 ,3.716 ,3.834 ,0.969 0 ,29 ,127 ,28 ,0 ,23 ,3.636 ,3.694 ,0.984 0 ,3 ,127 ,2 ,0 ,0 ,3.639 ,3.763 ,0.967 0 ,3 ,127 ,2 ,0 ,23 ,3.932 ,3.78 ,1.04 0 ,30 ,127 ,29 ,0 ,0 ,4.022 ,3.916 ,1.027 0 ,30 ,127 ,29 ,0 ,23 ,3.74 ,3.705 ,1.01 0 ,304 ,127 ,16 ,0 ,0 ,3.624 ,3.732 ,0.971 0 ,31 ,127 ,30 ,0 ,0 ,3.389 ,3.714 ,0.912 0 ,31 ,127 ,30 ,0 ,23 ,3.687 ,3.798 ,0.971 0 ,32 ,127 ,128 ,0 ,0 ,4.491 ,5.165 ,0.869 0 ,32 ,127 ,160 ,0 ,0 ,4.574 ,5.127 ,0.892 0 ,32 ,127 ,192 ,0 ,0 ,4.556 ,5.205 ,0.875 0 ,32 ,127 ,224 ,0 ,0 ,4.461 ,5.18 ,0.861 0 ,32 ,127 ,256 ,0 ,0 ,4.531 ,5.221 ,0.868 0 ,32 ,127 ,288 ,0 ,0 ,4.478 ,5.097 ,0.879 0 ,32 ,127 ,31 ,0 ,0 ,3.625 ,3.727 ,0.973 0 ,32 ,127 ,31 ,0 ,23 ,3.565 ,3.746 ,0.952 0 ,32 ,127 ,320 ,0 ,0 ,4.466 ,5.132 ,0.87 0 ,32 ,127 ,352 ,0 ,0 ,4.445 ,5.156 ,0.862 0 ,32 ,127 ,64 ,0 ,0 ,4.436 ,5.158 ,0.86 0 ,32 ,127 ,96 ,0 ,0 ,4.524 ,5.177 ,0.874 0 ,320 ,127 ,128 ,0 ,0 ,7.679 ,8.009 ,0.959 0 ,320 ,127 ,256 ,0 ,0 ,13.156 ,13.269 ,0.991 0 ,320 ,127 ,32 ,0 ,0 ,4.406 ,5.076 ,0.868 0 ,320 ,127 ,512 ,0 ,0 ,15.267 ,15.689 ,0.973 0 ,320 ,127 ,64 ,0 ,0 ,5.728 ,6.071 ,0.943 0 ,336 ,127 ,16 ,0 ,0 ,3.546 ,3.785 ,0.937 0 ,352 ,127 ,128 ,0 ,0 ,7.629 ,7.947 ,0.96 0 ,352 ,127 ,256 ,0 ,0 ,13.186 ,13.265 ,0.994 0 ,352 ,127 ,32 ,0 ,0 ,4.472 ,5.164 ,0.866 0 ,352 ,127 ,512 ,0 ,0 ,15.227 ,15.664 ,0.972 0 ,352 ,127 ,64 ,0 ,0 ,5.718 ,6.146 ,0.93 0 ,3776 ,127 ,4096 ,0 ,0 ,105.51 ,107.765 ,0.979 0 ,3808 ,127 ,4096 ,0 ,0 ,106.367 ,108.324 ,0.982 0 ,384 ,127 ,128 ,0 ,0 ,7.676 ,7.958 ,0.965 0 ,384 ,127 ,256 ,0 ,0 ,13.166 ,13.286 ,0.991 0 ,384 ,127 ,512 ,0 ,0 ,15.978 ,16.496 ,0.969 0 ,384 ,127 ,64 ,0 ,0 ,5.725 ,6.119 ,0.936 0 ,3840 ,127 ,4096 ,0 ,0 ,109.166 ,109.746 ,0.995 0 ,3872 ,127 ,4096 ,0 ,0 ,110.249 ,111.264 ,0.991 0 ,3904 ,127 ,4096 ,0 ,0 ,109.902 ,110.697 ,0.993 0 ,3936 ,127 ,4096 ,0 ,0 ,111.099 ,110.706 ,1.004 0 ,3968 ,127 ,4096 ,0 ,0 ,111.392 ,111.842 ,0.996 0 ,4 ,127 ,3 ,0 ,0 ,3.839 ,3.808 ,1.008 0 ,4 ,127 ,3 ,0 ,23 ,3.856 ,3.77 ,1.023 0 ,4000 ,127 ,4096 ,0 ,0 ,116.589 ,114.016 ,1.023 0 ,4032 ,127 ,4096 ,0 ,0 ,110.905 ,112.745 ,0.984 0 ,4064 ,127 ,4096 ,0 ,0 ,111.287 ,112.624 ,0.988 0 ,4096 ,127 ,1024 ,0 ,0 ,29.657 ,30.043 ,0.987 0 ,4096 ,127 ,1024 ,0 ,23 ,29.48 ,30.512 ,0.966 0 ,4096 ,127 ,128 ,0 ,0 ,7.7 ,7.971 ,0.966 0 ,4096 ,127 ,128 ,0 ,23 ,7.755 ,8.1 ,0.957 0 ,4096 ,127 ,2048 ,0 ,0 ,49.751 ,49.548 ,1.004 0 ,4096 ,127 ,2048 ,0 ,23 ,49.523 ,50.29 ,0.985 0 ,4096 ,127 ,256 ,0 ,0 ,13.245 ,13.453 ,0.985 0 ,4096 ,127 ,256 ,0 ,23 ,13.209 ,13.294 ,0.994 0 ,4096 ,127 ,32 ,0 ,0 ,4.265 ,5.024 ,0.849 0 ,4096 ,127 ,32 ,0 ,23 ,4.281 ,5.055 ,0.847 0 ,4096 ,127 ,3776 ,0 ,0 ,105.786 ,107.432 ,0.985 0 ,4096 ,127 ,3808 ,0 ,0 ,106.443 ,107.572 ,0.99 0 ,4096 ,127 ,3840 ,0 ,0 ,108.991 ,108.912 ,1.001 0 ,4096 ,127 ,3872 ,0 ,0 ,111.415 ,110.611 ,1.007 0 ,4096 ,127 ,3904 ,0 ,0 ,110.989 ,111.712 ,0.994 0 ,4096 ,127 ,3936 ,0 ,0 ,109.447 ,110.444 ,0.991 0 ,4096 ,127 ,3968 ,0 ,0 ,111.311 ,111.836 ,0.995 0 ,4096 ,127 ,4000 ,0 ,0 ,113.892 ,113.212 ,1.006 0 ,4096 ,127 ,4032 ,0 ,0 ,111.372 ,112.833 ,0.987 0 ,4096 ,127 ,4064 ,0 ,0 ,111.099 ,112.903 ,0.984 0 ,4096 ,127 ,4128 ,0 ,0 ,114.014 ,114.658 ,0.994 0 ,4096 ,127 ,4160 ,0 ,0 ,114.292 ,114.87 ,0.995 0 ,4096 ,127 ,4192 ,0 ,0 ,113.46 ,115.051 ,0.986 0 ,4096 ,127 ,4224 ,0 ,0 ,117.617 ,114.589 ,1.026 0 ,4096 ,127 ,4256 ,0 ,0 ,113.151 ,114.284 ,0.99 0 ,4096 ,127 ,4288 ,0 ,0 ,114.383 ,114.095 ,1.003 0 ,4096 ,127 ,4320 ,0 ,0 ,114.065 ,114.231 ,0.999 0 ,4096 ,127 ,4352 ,0 ,0 ,113.966 ,114.57 ,0.995 0 ,4096 ,127 ,4384 ,0 ,0 ,115.202 ,114.359 ,1.007 0 ,4096 ,127 ,4416 ,0 ,0 ,112.809 ,115.726 ,0.975 0 ,4096 ,127 ,512 ,0 ,0 ,18.721 ,19.765 ,0.947 0 ,4096 ,127 ,512 ,0 ,23 ,19.174 ,20.009 ,0.958 0 ,4096 ,127 ,64 ,0 ,0 ,5.695 ,6.177 ,0.922 0 ,4096 ,127 ,64 ,0 ,23 ,5.749 ,6.158 ,0.934 0 ,4128 ,127 ,4096 ,0 ,0 ,114.74 ,115.58 ,0.993 0 ,416 ,127 ,128 ,0 ,0 ,7.664 ,7.92 ,0.968 0 ,416 ,127 ,256 ,0 ,0 ,13.141 ,13.309 ,0.987 0 ,416 ,127 ,512 ,0 ,0 ,16.533 ,17.572 ,0.941 0 ,4160 ,127 ,4096 ,0 ,0 ,114.205 ,114.581 ,0.997 0 ,4192 ,127 ,4096 ,0 ,0 ,114.037 ,114.563 ,0.995 0 ,4224 ,127 ,4096 ,0 ,0 ,112.83 ,113.973 ,0.99 0 ,4256 ,127 ,4096 ,0 ,0 ,114.023 ,114.334 ,0.997 0 ,4288 ,127 ,4096 ,0 ,0 ,114.114 ,116.138 ,0.983 0 ,4320 ,127 ,4096 ,0 ,0 ,113.92 ,114.222 ,0.997 0 ,4352 ,127 ,4096 ,0 ,0 ,112.957 ,114.64 ,0.985 0 ,4384 ,127 ,4096 ,0 ,0 ,114.339 ,114.157 ,1.002 0 ,4416 ,127 ,4096 ,0 ,0 ,113.914 ,114.599 ,0.994 0 ,448 ,127 ,128 ,0 ,0 ,7.621 ,7.962 ,0.957 0 ,448 ,127 ,256 ,0 ,0 ,13.26 ,13.177 ,1.006 0 ,448 ,127 ,512 ,0 ,0 ,18.465 ,18.643 ,0.99 0 ,48 ,127 ,16 ,0 ,0 ,3.734 ,3.646 ,1.024 0 ,480 ,127 ,256 ,0 ,0 ,13.329 ,13.499 ,0.987 0 ,480 ,127 ,512 ,0 ,0 ,19.341 ,18.871 ,1.025 0 ,5 ,127 ,4 ,0 ,0 ,3.754 ,3.763 ,0.998 0 ,5 ,127 ,4 ,0 ,23 ,3.765 ,3.751 ,1.004 0 ,512 ,127 ,192 ,0 ,0 ,12.734 ,13.07 ,0.974 0 ,512 ,127 ,224 ,0 ,0 ,12.673 ,12.963 ,0.978 0 ,512 ,127 ,256 ,0 ,0 ,12.912 ,13.061 ,0.989 0 ,512 ,127 ,256 ,0 ,23 ,13.257 ,13.38 ,0.991 0 ,512 ,127 ,288 ,0 ,0 ,13.901 ,14.448 ,0.962 0 ,512 ,127 ,320 ,0 ,0 ,15.205 ,15.713 ,0.968 0 ,512 ,127 ,352 ,0 ,0 ,15.225 ,15.747 ,0.967 0 ,512 ,127 ,384 ,0 ,0 ,15.999 ,16.379 ,0.977 0 ,512 ,127 ,416 ,0 ,0 ,16.328 ,17.508 ,0.933 0 ,512 ,127 ,448 ,0 ,0 ,18.029 ,18.544 ,0.972 0 ,512 ,127 ,480 ,0 ,0 ,18.664 ,18.775 ,0.994 0 ,512 ,127 ,544 ,0 ,0 ,18.686 ,19.64 ,0.951 0 ,512 ,127 ,576 ,0 ,0 ,18.776 ,19.686 ,0.954 0 ,512 ,127 ,608 ,0 ,0 ,18.678 ,19.647 ,0.951 0 ,512 ,127 ,640 ,0 ,0 ,18.757 ,19.616 ,0.956 0 ,512 ,127 ,672 ,0 ,0 ,18.745 ,19.624 ,0.955 0 ,512 ,127 ,704 ,0 ,0 ,18.672 ,19.656 ,0.95 0 ,512 ,127 ,736 ,0 ,0 ,18.718 ,19.674 ,0.951 0 ,512 ,127 ,768 ,0 ,0 ,18.952 ,19.726 ,0.961 0 ,512 ,127 ,800 ,0 ,0 ,18.774 ,19.765 ,0.95 0 ,512 ,127 ,832 ,0 ,0 ,18.699 ,19.706 ,0.949 0 ,544 ,127 ,256 ,0 ,0 ,13.279 ,13.418 ,0.99 0 ,544 ,127 ,512 ,0 ,0 ,19.074 ,19.752 ,0.966 0 ,576 ,127 ,256 ,0 ,0 ,13.238 ,13.385 ,0.989 0 ,576 ,127 ,512 ,0 ,0 ,19.177 ,19.701 ,0.973 0 ,6 ,127 ,5 ,0 ,0 ,3.836 ,3.797 ,1.01 0 ,6 ,127 ,5 ,0 ,23 ,3.777 ,3.786 ,0.997 0 ,608 ,127 ,512 ,0 ,0 ,19.094 ,19.804 ,0.964 0 ,64 ,127 ,128 ,0 ,0 ,5.722 ,6.174 ,0.927 0 ,64 ,127 ,160 ,0 ,0 ,5.765 ,6.12 ,0.942 0 ,64 ,127 ,192 ,0 ,0 ,5.737 ,6.173 ,0.929 0 ,64 ,127 ,224 ,0 ,0 ,5.734 ,6.125 ,0.936 0 ,64 ,127 ,256 ,0 ,0 ,5.721 ,6.158 ,0.929 0 ,64 ,127 ,288 ,0 ,0 ,5.718 ,6.165 ,0.928 0 ,64 ,127 ,32 ,0 ,0 ,4.61 ,5.286 ,0.872 0 ,64 ,127 ,320 ,0 ,0 ,5.731 ,6.134 ,0.934 0 ,64 ,127 ,352 ,0 ,0 ,5.725 ,6.088 ,0.94 0 ,64 ,127 ,384 ,0 ,0 ,5.681 ,6.04 ,0.94 0 ,64 ,127 ,96 ,0 ,0 ,5.721 ,6.103 ,0.937 0 ,640 ,127 ,512 ,0 ,0 ,18.698 ,20.357 ,0.918 0 ,672 ,127 ,512 ,0 ,0 ,18.702 ,19.702 ,0.949 0 ,7 ,127 ,6 ,0 ,0 ,3.805 ,3.745 ,1.016 0 ,7 ,127 ,6 ,0 ,23 ,3.839 ,3.669 ,1.046 0 ,704 ,127 ,1024 ,0 ,0 ,23.955 ,24.068 ,0.995 0 ,704 ,127 ,512 ,0 ,0 ,18.759 ,19.622 ,0.956 0 ,736 ,127 ,1024 ,0 ,0 ,24.345 ,24.028 ,1.013 0 ,736 ,127 ,512 ,0 ,0 ,18.668 ,19.678 ,0.949 0 ,768 ,127 ,1024 ,0 ,0 ,23.966 ,24.134 ,0.993 0 ,768 ,127 ,512 ,0 ,0 ,18.792 ,19.694 ,0.954 0 ,7872 ,127 ,8192 ,0 ,0 ,188.906 ,188.92 ,1.0 0 ,7904 ,127 ,8192 ,0 ,0 ,188.558 ,189.02 ,0.998 0 ,7936 ,127 ,8192 ,0 ,0 ,192.26 ,190.741 ,1.008 0 ,7968 ,127 ,8192 ,0 ,0 ,193.974 ,190.979 ,1.016 0 ,8 ,127 ,7 ,0 ,0 ,3.744 ,3.69 ,1.015 0 ,8 ,127 ,7 ,0 ,23 ,3.796 ,3.749 ,1.013 0 ,80 ,127 ,16 ,0 ,0 ,3.555 ,3.815 ,0.932 0 ,800 ,127 ,1024 ,0 ,0 ,25.005 ,25.674 ,0.974 0 ,800 ,127 ,512 ,0 ,0 ,19.018 ,19.747 ,0.963 0 ,8000 ,127 ,8192 ,0 ,0 ,191.652 ,192.035 ,0.998 0 ,8032 ,127 ,8192 ,0 ,0 ,191.076 ,191.566 ,0.997 0 ,8064 ,127 ,8192 ,0 ,0 ,193.207 ,193.492 ,0.999 0 ,8096 ,127 ,8192 ,0 ,0 ,197.26 ,193.563 ,1.019 0 ,8128 ,127 ,8192 ,0 ,0 ,193.573 ,193.812 ,0.999 0 ,8160 ,127 ,8192 ,0 ,0 ,193.447 ,193.887 ,0.998 0 ,832 ,127 ,1024 ,0 ,0 ,26.586 ,27.037 ,0.983 0 ,832 ,127 ,512 ,0 ,0 ,18.694 ,19.728 ,0.948 0 ,864 ,127 ,1024 ,0 ,0 ,26.631 ,26.966 ,0.988 0 ,896 ,127 ,1024 ,0 ,0 ,26.344 ,26.579 ,0.991 0 ,9 ,127 ,8 ,0 ,0 ,3.743 ,3.787 ,0.988 0 ,9 ,127 ,8 ,0 ,23 ,3.805 ,3.726 ,1.021 0 ,928 ,127 ,1024 ,0 ,0 ,27.017 ,28.306 ,0.954 0 ,96 ,127 ,128 ,0 ,0 ,6.253 ,6.449 ,0.97 0 ,96 ,127 ,256 ,0 ,0 ,6.283 ,6.457 ,0.973 0 ,96 ,127 ,32 ,0 ,0 ,4.546 ,5.143 ,0.884 0 ,96 ,127 ,64 ,0 ,0 ,5.726 ,6.18 ,0.927 0 ,960 ,127 ,1024 ,0 ,0 ,28.882 ,29.824 ,0.968 0 ,992 ,127 ,1024 ,0 ,0 ,29.47 ,30.002 ,0.982 1 ,2048 ,127 ,32 ,0 ,0 ,4.496 ,5.184 ,0.867 1 ,2048 ,127 ,32 ,0 ,23 ,4.364 ,5.121 ,0.852 1 ,256 ,127 ,64 ,0 ,0 ,5.633 ,6.061 ,0.929 1 ,256 ,127 ,64 ,0 ,23 ,5.673 ,6.14 ,0.924 1 ,4096 ,127 ,32 ,0 ,0 ,4.362 ,5.109 ,0.854 1 ,4096 ,127 ,32 ,0 ,23 ,4.38 ,5.189 ,0.844 112 ,512 ,127 ,256 ,0 ,0 ,12.498 ,13.087 ,0.955 112 ,512 ,127 ,256 ,0 ,23 ,12.488 ,13.024 ,0.959 16 ,512 ,127 ,256 ,0 ,0 ,13.162 ,13.325 ,0.988 16 ,512 ,127 ,256 ,0 ,23 ,13.287 ,13.397 ,0.992 2 ,2048 ,127 ,64 ,0 ,0 ,5.794 ,6.136 ,0.944 2 ,2048 ,127 ,64 ,0 ,23 ,6.643 ,6.347 ,1.047 2 ,256 ,127 ,64 ,0 ,0 ,5.804 ,6.116 ,0.949 2 ,256 ,127 ,64 ,0 ,23 ,5.749 ,6.133 ,0.937 2 ,4096 ,127 ,64 ,0 ,0 ,5.723 ,6.136 ,0.933 2 ,4096 ,127 ,64 ,0 ,23 ,5.746 ,6.145 ,0.935 3 ,2048 ,127 ,128 ,0 ,0 ,7.751 ,7.978 ,0.972 3 ,2048 ,127 ,128 ,0 ,23 ,7.715 ,7.908 ,0.976 3 ,256 ,127 ,64 ,0 ,0 ,5.748 ,6.085 ,0.945 3 ,256 ,127 ,64 ,0 ,23 ,5.769 ,6.148 ,0.938 3 ,4096 ,127 ,128 ,0 ,0 ,7.743 ,7.953 ,0.974 3 ,4096 ,127 ,128 ,0 ,23 ,7.778 ,7.967 ,0.976 32 ,512 ,127 ,256 ,0 ,0 ,13.969 ,14.553 ,0.96 32 ,512 ,127 ,256 ,0 ,23 ,14.077 ,14.603 ,0.964 4 ,2048 ,127 ,256 ,0 ,0 ,13.278 ,13.426 ,0.989 4 ,2048 ,127 ,256 ,0 ,23 ,13.228 ,13.339 ,0.992 4 ,256 ,127 ,64 ,0 ,0 ,5.768 ,6.178 ,0.934 4 ,256 ,127 ,64 ,0 ,23 ,5.735 ,6.178 ,0.928 4 ,4096 ,127 ,256 ,0 ,0 ,13.149 ,13.324 ,0.987 4 ,4096 ,127 ,256 ,0 ,23 ,13.294 ,13.347 ,0.996 48 ,512 ,127 ,256 ,0 ,0 ,14.041 ,14.585 ,0.963 48 ,512 ,127 ,256 ,0 ,23 ,14.077 ,14.604 ,0.964 5 ,2048 ,127 ,512 ,0 ,0 ,18.994 ,19.767 ,0.961 5 ,2048 ,127 ,512 ,0 ,23 ,18.849 ,19.714 ,0.956 5 ,256 ,127 ,64 ,0 ,0 ,5.781 ,6.154 ,0.939 5 ,256 ,127 ,64 ,0 ,23 ,5.765 ,6.127 ,0.941 5 ,4096 ,127 ,512 ,0 ,0 ,18.798 ,19.661 ,0.956 5 ,4096 ,127 ,512 ,0 ,23 ,18.791 ,19.726 ,0.953 6 ,2048 ,127 ,1024 ,0 ,0 ,29.292 ,29.622 ,0.989 6 ,2048 ,127 ,1024 ,0 ,23 ,29.479 ,29.791 ,0.99 6 ,256 ,127 ,64 ,0 ,0 ,5.757 ,6.182 ,0.931 6 ,256 ,127 ,64 ,0 ,23 ,5.752 ,6.147 ,0.936 6 ,4096 ,127 ,1024 ,0 ,0 ,29.127 ,29.948 ,0.973 6 ,4096 ,127 ,1024 ,0 ,23 ,29.61 ,29.72 ,0.996 64 ,512 ,127 ,256 ,0 ,0 ,15.276 ,15.847 ,0.964 64 ,512 ,127 ,256 ,0 ,23 ,15.232 ,15.837 ,0.962 7 ,2048 ,127 ,2048 ,0 ,0 ,49.456 ,49.464 ,1.0 7 ,2048 ,127 ,2048 ,0 ,23 ,49.474 ,49.562 ,0.998 7 ,256 ,127 ,64 ,0 ,0 ,5.719 ,6.138 ,0.932 7 ,256 ,127 ,64 ,0 ,23 ,5.827 ,6.498 ,0.897 7 ,4096 ,127 ,2048 ,0 ,0 ,49.453 ,49.364 ,1.002 7 ,4096 ,127 ,2048 ,0 ,23 ,49.621 ,49.647 ,0.999 80 ,512 ,127 ,256 ,0 ,0 ,15.222 ,15.796 ,0.964 80 ,512 ,127 ,256 ,0 ,23 ,15.275 ,15.819 ,0.966 96 ,512 ,127 ,256 ,0 ,0 ,12.366 ,12.833 ,0.964 96 ,512 ,127 ,256 ,0 ,23 ,12.363 ,12.934 ,0.956 alignment,branch ,length ,perc-zero ,pos ,rand ,__strchr_evex ,__strchr_evex_orig 0 ,0 ,16 ,0 ,15 ,1 ,4.172 ,4.532 ,0.92 0 ,0 ,16 ,0.1 ,15 ,1 ,4.151 ,4.495 ,0.923 0 ,0 ,16 ,0.25 ,15 ,1 ,4.152 ,4.413 ,0.941 0 ,0 ,16 ,0.33 ,15 ,1 ,4.045 ,4.481 ,0.903 0 ,0 ,16 ,0.5 ,15 ,1 ,4.055 ,4.396 ,0.922 0 ,0 ,16 ,0.66 ,15 ,1 ,4.113 ,4.432 ,0.928 0 ,0 ,16 ,0.75 ,15 ,1 ,4.053 ,4.353 ,0.931 0 ,0 ,16 ,0.9 ,15 ,1 ,4.183 ,4.467 ,0.936 0 ,0 ,16 ,1 ,15 ,1 ,4.194 ,4.41 ,0.951 0 ,1 ,16 ,0 ,15 ,1 ,3.834 ,4.118 ,0.931 0 ,1 ,16 ,0.1 ,15 ,1 ,4.129 ,4.454 ,0.927 0 ,1 ,16 ,0.25 ,15 ,1 ,4.118 ,4.446 ,0.926 0 ,1 ,16 ,0.33 ,15 ,1 ,4.134 ,4.357 ,0.949 0 ,1 ,16 ,0.5 ,15 ,1 ,4.073 ,4.441 ,0.917 0 ,1 ,16 ,0.66 ,15 ,1 ,4.146 ,4.294 ,0.965 0 ,1 ,16 ,0.75 ,15 ,1 ,4.009 ,4.295 ,0.934 0 ,1 ,16 ,0.9 ,15 ,1 ,4.106 ,4.398 ,0.934 0 ,1 ,16 ,1 ,15 ,1 ,4.176 ,4.474 ,0.933 0.9711578243606377 0.9316238188843593 Results For: strchrnul alignment,length ,max_char ,pos ,rand ,seek_char ,__strchrnul_evex ,__strchrnul_evex_orig 0 ,1 ,127 ,0 ,0 ,0 ,3.278 ,3.518 ,0.932 0 ,1 ,127 ,0 ,0 ,23 ,3.361 ,3.484 ,0.965 0 ,10 ,127 ,9 ,0 ,0 ,3.536 ,3.875 ,0.913 0 ,10 ,127 ,9 ,0 ,23 ,3.504 ,3.848 ,0.911 0 ,1024 ,127 ,1056 ,0 ,0 ,27.379 ,28.047 ,0.976 0 ,1024 ,127 ,1088 ,0 ,0 ,27.769 ,27.969 ,0.993 0 ,1024 ,127 ,1120 ,0 ,0 ,27.693 ,28.098 ,0.986 0 ,1024 ,127 ,1152 ,0 ,0 ,27.515 ,27.972 ,0.984 0 ,1024 ,127 ,1184 ,0 ,0 ,27.754 ,28.04 ,0.99 0 ,1024 ,127 ,1216 ,0 ,0 ,27.505 ,27.97 ,0.983 0 ,1024 ,127 ,1248 ,0 ,0 ,27.209 ,28.032 ,0.971 0 ,1024 ,127 ,1280 ,0 ,0 ,27.272 ,28.006 ,0.974 0 ,1024 ,127 ,1312 ,0 ,0 ,27.439 ,28.208 ,0.973 0 ,1024 ,127 ,1344 ,0 ,0 ,27.735 ,28.267 ,0.981 0 ,1024 ,127 ,704 ,0 ,0 ,23.327 ,22.756 ,1.025 0 ,1024 ,127 ,736 ,0 ,0 ,23.564 ,22.933 ,1.028 0 ,1024 ,127 ,768 ,0 ,0 ,22.939 ,23.247 ,0.987 0 ,1024 ,127 ,800 ,0 ,0 ,25.721 ,23.809 ,1.08 0 ,1024 ,127 ,832 ,0 ,0 ,26.317 ,25.581 ,1.029 0 ,1024 ,127 ,864 ,0 ,0 ,26.403 ,25.816 ,1.023 0 ,1024 ,127 ,896 ,0 ,0 ,25.478 ,25.882 ,0.984 0 ,1024 ,127 ,928 ,0 ,0 ,27.202 ,26.707 ,1.019 0 ,1024 ,127 ,960 ,0 ,0 ,28.797 ,28.491 ,1.011 0 ,1024 ,127 ,992 ,0 ,0 ,28.914 ,28.424 ,1.017 0 ,1056 ,127 ,1024 ,0 ,0 ,27.875 ,28.307 ,0.985 0 ,1088 ,127 ,1024 ,0 ,0 ,27.721 ,28.452 ,0.974 0 ,11 ,127 ,10 ,0 ,0 ,3.527 ,3.86 ,0.914 0 ,11 ,127 ,10 ,0 ,23 ,3.522 ,3.73 ,0.944 0 ,112 ,127 ,16 ,0 ,0 ,3.339 ,3.913 ,0.853 0 ,1120 ,127 ,1024 ,0 ,0 ,28.622 ,28.123 ,1.018 0 ,1152 ,127 ,1024 ,0 ,0 ,27.549 ,27.931 ,0.986 0 ,1184 ,127 ,1024 ,0 ,0 ,27.42 ,28.076 ,0.977 0 ,12 ,127 ,11 ,0 ,0 ,3.514 ,3.837 ,0.916 0 ,12 ,127 ,11 ,0 ,23 ,3.429 ,3.846 ,0.892 0 ,1216 ,127 ,1024 ,0 ,0 ,27.451 ,28.133 ,0.976 0 ,1248 ,127 ,1024 ,0 ,0 ,27.235 ,28.012 ,0.972 0 ,128 ,127 ,160 ,0 ,0 ,7.064 ,7.304 ,0.967 0 ,128 ,127 ,192 ,0 ,0 ,7.042 ,7.337 ,0.96 0 ,128 ,127 ,224 ,0 ,0 ,7.075 ,7.344 ,0.963 0 ,128 ,127 ,256 ,0 ,0 ,7.066 ,7.338 ,0.963 0 ,128 ,127 ,288 ,0 ,0 ,7.054 ,7.338 ,0.961 0 ,128 ,127 ,32 ,0 ,0 ,4.748 ,4.967 ,0.956 0 ,128 ,127 ,320 ,0 ,0 ,7.061 ,7.285 ,0.969 0 ,128 ,127 ,352 ,0 ,0 ,7.104 ,7.342 ,0.968 0 ,128 ,127 ,384 ,0 ,0 ,7.133 ,7.472 ,0.955 0 ,128 ,127 ,416 ,0 ,0 ,7.017 ,7.321 ,0.958 0 ,128 ,127 ,448 ,0 ,0 ,7.065 ,7.341 ,0.962 0 ,128 ,127 ,64 ,0 ,0 ,5.224 ,5.743 ,0.91 0 ,128 ,127 ,96 ,0 ,0 ,5.969 ,6.206 ,0.962 0 ,1280 ,127 ,1024 ,0 ,0 ,27.438 ,27.981 ,0.981 0 ,13 ,127 ,12 ,0 ,0 ,3.56 ,3.838 ,0.927 0 ,13 ,127 ,12 ,0 ,23 ,3.559 ,3.879 ,0.917 0 ,1312 ,127 ,1024 ,0 ,0 ,27.522 ,28.385 ,0.97 0 ,1344 ,127 ,1024 ,0 ,0 ,27.53 ,28.04 ,0.982 0 ,14 ,127 ,13 ,0 ,0 ,3.483 ,3.916 ,0.889 0 ,14 ,127 ,13 ,0 ,23 ,3.472 ,3.916 ,0.887 0 ,144 ,127 ,16 ,0 ,0 ,3.485 ,3.975 ,0.877 0 ,15 ,127 ,14 ,0 ,0 ,3.467 ,3.859 ,0.898 0 ,15 ,127 ,14 ,0 ,23 ,3.533 ,3.92 ,0.901 0 ,16 ,127 ,112 ,0 ,0 ,3.471 ,3.855 ,0.9 0 ,16 ,127 ,144 ,0 ,0 ,3.417 ,3.839 ,0.89 0 ,16 ,127 ,15 ,0 ,0 ,3.479 ,3.924 ,0.887 0 ,16 ,127 ,15 ,0 ,23 ,3.482 ,3.885 ,0.896 0 ,16 ,127 ,176 ,0 ,0 ,3.526 ,3.868 ,0.912 0 ,16 ,127 ,208 ,0 ,0 ,3.574 ,4.006 ,0.892 0 ,16 ,127 ,240 ,0 ,0 ,3.44 ,3.907 ,0.88 0 ,16 ,127 ,272 ,0 ,0 ,3.473 ,3.958 ,0.877 0 ,16 ,127 ,304 ,0 ,0 ,3.394 ,3.924 ,0.865 0 ,16 ,127 ,336 ,0 ,0 ,3.499 ,3.875 ,0.903 0 ,16 ,127 ,48 ,0 ,0 ,3.319 ,3.769 ,0.88 0 ,16 ,127 ,80 ,0 ,0 ,3.392 ,3.901 ,0.87 0 ,160 ,127 ,128 ,0 ,0 ,7.183 ,7.334 ,0.979 0 ,160 ,127 ,256 ,0 ,0 ,10.851 ,10.975 ,0.989 0 ,160 ,127 ,32 ,0 ,0 ,4.642 ,4.577 ,1.014 0 ,160 ,127 ,64 ,0 ,0 ,5.258 ,5.725 ,0.918 0 ,17 ,127 ,16 ,0 ,0 ,3.518 ,3.895 ,0.903 0 ,17 ,127 ,16 ,0 ,23 ,3.452 ,3.94 ,0.876 0 ,1728 ,127 ,2048 ,0 ,0 ,44.006 ,43.637 ,1.008 0 ,176 ,127 ,16 ,0 ,0 ,3.397 ,3.829 ,0.887 0 ,1760 ,127 ,2048 ,0 ,0 ,44.426 ,43.129 ,1.03 0 ,1792 ,127 ,2048 ,0 ,0 ,43.072 ,44.071 ,0.977 0 ,18 ,127 ,17 ,0 ,0 ,3.514 ,3.861 ,0.91 0 ,18 ,127 ,17 ,0 ,23 ,3.491 ,3.839 ,0.91 0 ,1824 ,127 ,2048 ,0 ,0 ,44.994 ,44.676 ,1.007 0 ,1856 ,127 ,2048 ,0 ,0 ,46.447 ,45.904 ,1.012 0 ,1888 ,127 ,2048 ,0 ,0 ,46.266 ,47.06 ,0.983 0 ,19 ,127 ,18 ,0 ,0 ,3.392 ,3.884 ,0.873 0 ,19 ,127 ,18 ,0 ,23 ,3.572 ,3.859 ,0.925 0 ,192 ,127 ,128 ,0 ,0 ,7.063 ,7.296 ,0.968 0 ,192 ,127 ,256 ,0 ,0 ,12.113 ,12.303 ,0.985 0 ,192 ,127 ,32 ,0 ,0 ,4.606 ,4.526 ,1.018 0 ,192 ,127 ,512 ,0 ,0 ,12.33 ,12.393 ,0.995 0 ,192 ,127 ,64 ,0 ,0 ,5.249 ,5.627 ,0.933 0 ,1920 ,127 ,2048 ,0 ,0 ,45.169 ,45.434 ,0.994 0 ,1952 ,127 ,2048 ,0 ,0 ,46.968 ,46.56 ,1.009 0 ,1984 ,127 ,2048 ,0 ,0 ,48.746 ,48.556 ,1.004 0 ,2 ,127 ,1 ,0 ,0 ,3.322 ,3.55 ,0.936 0 ,2 ,127 ,1 ,0 ,23 ,3.54 ,3.6 ,0.983 0 ,20 ,127 ,19 ,0 ,0 ,3.424 ,3.885 ,0.881 0 ,20 ,127 ,19 ,0 ,23 ,3.402 ,3.925 ,0.867 0 ,2016 ,127 ,2048 ,0 ,0 ,48.746 ,48.314 ,1.009 0 ,2048 ,127 ,1024 ,0 ,0 ,27.64 ,28.634 ,0.965 0 ,2048 ,127 ,1024 ,0 ,23 ,27.678 ,28.285 ,0.979 0 ,2048 ,127 ,128 ,0 ,0 ,7.006 ,7.284 ,0.962 0 ,2048 ,127 ,128 ,0 ,23 ,7.306 ,7.942 ,0.92 0 ,2048 ,127 ,1728 ,0 ,0 ,44.065 ,43.587 ,1.011 0 ,2048 ,127 ,1760 ,0 ,0 ,43.92 ,43.199 ,1.017 0 ,2048 ,127 ,1792 ,0 ,0 ,43.424 ,43.32 ,1.002 0 ,2048 ,127 ,1824 ,0 ,0 ,44.812 ,43.868 ,1.022 0 ,2048 ,127 ,1856 ,0 ,0 ,46.22 ,45.548 ,1.015 0 ,2048 ,127 ,1888 ,0 ,0 ,46.415 ,45.692 ,1.016 0 ,2048 ,127 ,1920 ,0 ,0 ,45.27 ,45.443 ,0.996 0 ,2048 ,127 ,1952 ,0 ,0 ,47.135 ,46.583 ,1.012 0 ,2048 ,127 ,1984 ,0 ,0 ,49.092 ,48.104 ,1.021 0 ,2048 ,127 ,2016 ,0 ,0 ,49.169 ,48.166 ,1.021 0 ,2048 ,127 ,2048 ,0 ,0 ,50.101 ,49.82 ,1.006 0 ,2048 ,127 ,2048 ,0 ,23 ,48.06 ,48.231 ,0.996 0 ,2048 ,127 ,2080 ,0 ,0 ,48.992 ,48.394 ,1.012 0 ,2048 ,127 ,2112 ,0 ,0 ,48.227 ,48.29 ,0.999 0 ,2048 ,127 ,2144 ,0 ,0 ,48.0 ,48.069 ,0.999 0 ,2048 ,127 ,2176 ,0 ,0 ,48.046 ,47.876 ,1.004 0 ,2048 ,127 ,2208 ,0 ,0 ,48.293 ,50.406 ,0.958 0 ,2048 ,127 ,2240 ,0 ,0 ,48.085 ,47.981 ,1.002 0 ,2048 ,127 ,2272 ,0 ,0 ,47.946 ,48.359 ,0.991 0 ,2048 ,127 ,2304 ,0 ,0 ,47.888 ,48.39 ,0.99 0 ,2048 ,127 ,2336 ,0 ,0 ,48.161 ,48.024 ,1.003 0 ,2048 ,127 ,2368 ,0 ,0 ,47.996 ,47.979 ,1.0 0 ,2048 ,127 ,256 ,0 ,0 ,12.933 ,13.158 ,0.983 0 ,2048 ,127 ,256 ,0 ,23 ,13.021 ,13.142 ,0.991 0 ,2048 ,127 ,32 ,0 ,0 ,4.701 ,4.704 ,0.999 0 ,2048 ,127 ,32 ,0 ,23 ,4.691 ,4.529 ,1.036 0 ,2048 ,127 ,512 ,0 ,0 ,18.465 ,18.891 ,0.977 0 ,2048 ,127 ,512 ,0 ,23 ,18.035 ,18.838 ,0.957 0 ,2048 ,127 ,64 ,0 ,0 ,5.34 ,5.647 ,0.946 0 ,2048 ,127 ,64 ,0 ,23 ,5.25 ,5.543 ,0.947 0 ,208 ,127 ,16 ,0 ,0 ,3.469 ,3.856 ,0.9 0 ,2080 ,127 ,2048 ,0 ,0 ,48.121 ,48.004 ,1.002 0 ,21 ,127 ,20 ,0 ,0 ,3.356 ,3.874 ,0.866 0 ,21 ,127 ,20 ,0 ,23 ,3.382 ,3.91 ,0.865 0 ,2112 ,127 ,2048 ,0 ,0 ,48.191 ,48.216 ,0.999 0 ,2144 ,127 ,2048 ,0 ,0 ,47.773 ,48.086 ,0.993 0 ,2176 ,127 ,2048 ,0 ,0 ,48.646 ,48.115 ,1.011 0 ,22 ,127 ,21 ,0 ,0 ,3.424 ,3.927 ,0.872 0 ,22 ,127 ,21 ,0 ,23 ,3.35 ,3.872 ,0.865 0 ,2208 ,127 ,2048 ,0 ,0 ,48.158 ,48.111 ,1.001 0 ,224 ,127 ,128 ,0 ,0 ,7.119 ,7.292 ,0.976 0 ,224 ,127 ,256 ,0 ,0 ,12.252 ,12.207 ,1.004 0 ,224 ,127 ,32 ,0 ,0 ,4.612 ,4.608 ,1.001 0 ,224 ,127 ,512 ,0 ,0 ,12.195 ,12.268 ,0.994 0 ,224 ,127 ,64 ,0 ,0 ,5.215 ,5.72 ,0.912 0 ,2240 ,127 ,2048 ,0 ,0 ,47.999 ,47.936 ,1.001 0 ,2272 ,127 ,2048 ,0 ,0 ,48.9 ,47.945 ,1.02 0 ,23 ,127 ,22 ,0 ,0 ,3.421 ,3.869 ,0.884 0 ,23 ,127 ,22 ,0 ,23 ,3.351 ,3.935 ,0.852 0 ,2304 ,127 ,2048 ,0 ,0 ,48.037 ,48.658 ,0.987 0 ,2336 ,127 ,2048 ,0 ,0 ,48.418 ,48.175 ,1.005 0 ,2368 ,127 ,2048 ,0 ,0 ,47.82 ,48.381 ,0.988 0 ,24 ,127 ,23 ,0 ,0 ,3.369 ,3.863 ,0.872 0 ,24 ,127 ,23 ,0 ,23 ,3.366 ,3.847 ,0.875 0 ,240 ,127 ,16 ,0 ,0 ,3.385 ,3.917 ,0.864 0 ,25 ,127 ,24 ,0 ,0 ,3.379 ,3.827 ,0.883 0 ,25 ,127 ,24 ,0 ,23 ,3.381 ,3.879 ,0.872 0 ,256 ,127 ,128 ,0 ,0 ,7.071 ,7.284 ,0.971 0 ,256 ,127 ,160 ,0 ,0 ,10.739 ,10.904 ,0.985 0 ,256 ,127 ,192 ,0 ,0 ,12.189 ,12.179 ,1.001 0 ,256 ,127 ,224 ,0 ,0 ,12.123 ,12.175 ,0.996 0 ,256 ,127 ,288 ,0 ,0 ,13.003 ,13.249 ,0.981 0 ,256 ,127 ,32 ,0 ,0 ,4.637 ,4.618 ,1.004 0 ,256 ,127 ,320 ,0 ,0 ,12.939 ,13.124 ,0.986 0 ,256 ,127 ,352 ,0 ,0 ,12.896 ,13.169 ,0.979 0 ,256 ,127 ,384 ,0 ,0 ,12.988 ,13.192 ,0.985 0 ,256 ,127 ,416 ,0 ,0 ,13.026 ,13.225 ,0.985 0 ,256 ,127 ,448 ,0 ,0 ,12.931 ,13.129 ,0.985 0 ,256 ,127 ,480 ,0 ,0 ,13.054 ,13.158 ,0.992 0 ,256 ,127 ,512 ,0 ,0 ,13.007 ,13.227 ,0.983 0 ,256 ,127 ,544 ,0 ,0 ,12.966 ,13.177 ,0.984 0 ,256 ,127 ,576 ,0 ,0 ,12.959 ,13.112 ,0.988 0 ,256 ,127 ,64 ,0 ,0 ,5.231 ,5.695 ,0.918 0 ,256 ,127 ,96 ,0 ,0 ,5.96 ,6.268 ,0.951 0 ,26 ,127 ,25 ,0 ,0 ,3.347 ,3.807 ,0.879 0 ,26 ,127 ,25 ,0 ,23 ,3.367 ,3.813 ,0.883 0 ,27 ,127 ,26 ,0 ,0 ,3.424 ,3.858 ,0.888 0 ,27 ,127 ,26 ,0 ,23 ,3.348 ,3.806 ,0.879 0 ,272 ,127 ,16 ,0 ,0 ,3.49 ,3.851 ,0.906 0 ,28 ,127 ,27 ,0 ,0 ,3.355 ,3.779 ,0.888 0 ,28 ,127 ,27 ,0 ,23 ,3.353 ,3.788 ,0.885 0 ,288 ,127 ,128 ,0 ,0 ,7.067 ,7.332 ,0.964 0 ,288 ,127 ,256 ,0 ,0 ,13.022 ,13.165 ,0.989 0 ,288 ,127 ,32 ,0 ,0 ,4.59 ,4.579 ,1.002 0 ,288 ,127 ,512 ,0 ,0 ,14.011 ,14.077 ,0.995 0 ,288 ,127 ,64 ,0 ,0 ,5.217 ,5.7 ,0.915 0 ,29 ,127 ,28 ,0 ,0 ,3.374 ,3.861 ,0.874 0 ,29 ,127 ,28 ,0 ,23 ,3.343 ,3.817 ,0.876 0 ,3 ,127 ,2 ,0 ,0 ,3.46 ,3.611 ,0.958 0 ,3 ,127 ,2 ,0 ,23 ,3.457 ,3.656 ,0.946 0 ,30 ,127 ,29 ,0 ,0 ,3.294 ,3.832 ,0.86 0 ,30 ,127 ,29 ,0 ,23 ,3.255 ,3.831 ,0.85 0 ,304 ,127 ,16 ,0 ,0 ,3.488 ,3.933 ,0.887 0 ,31 ,127 ,30 ,0 ,0 ,3.261 ,3.747 ,0.87 0 ,31 ,127 ,30 ,0 ,23 ,3.173 ,3.781 ,0.839 0 ,32 ,127 ,128 ,0 ,0 ,4.607 ,4.599 ,1.002 0 ,32 ,127 ,160 ,0 ,0 ,4.618 ,4.622 ,0.999 0 ,32 ,127 ,192 ,0 ,0 ,4.592 ,4.602 ,0.998 0 ,32 ,127 ,224 ,0 ,0 ,4.659 ,4.554 ,1.023 0 ,32 ,127 ,256 ,0 ,0 ,4.627 ,4.679 ,0.989 0 ,32 ,127 ,288 ,0 ,0 ,4.621 ,4.613 ,1.002 0 ,32 ,127 ,31 ,0 ,0 ,3.261 ,3.685 ,0.885 0 ,32 ,127 ,31 ,0 ,23 ,3.135 ,3.756 ,0.835 0 ,32 ,127 ,320 ,0 ,0 ,4.605 ,4.586 ,1.004 0 ,32 ,127 ,352 ,0 ,0 ,4.618 ,4.614 ,1.001 0 ,32 ,127 ,64 ,0 ,0 ,4.668 ,4.695 ,0.994 0 ,32 ,127 ,96 ,0 ,0 ,4.594 ,4.567 ,1.006 0 ,320 ,127 ,128 ,0 ,0 ,7.089 ,7.334 ,0.967 0 ,320 ,127 ,256 ,0 ,0 ,12.997 ,13.234 ,0.982 0 ,320 ,127 ,32 ,0 ,0 ,4.63 ,4.598 ,1.007 0 ,320 ,127 ,512 ,0 ,0 ,15.176 ,14.995 ,1.012 0 ,320 ,127 ,64 ,0 ,0 ,5.225 ,5.715 ,0.914 0 ,336 ,127 ,16 ,0 ,0 ,3.409 ,3.886 ,0.877 0 ,352 ,127 ,128 ,0 ,0 ,7.069 ,7.33 ,0.964 0 ,352 ,127 ,256 ,0 ,0 ,12.825 ,13.147 ,0.975 0 ,352 ,127 ,32 ,0 ,0 ,4.599 ,4.572 ,1.006 0 ,352 ,127 ,512 ,0 ,0 ,15.347 ,15.141 ,1.014 0 ,352 ,127 ,64 ,0 ,0 ,5.441 ,5.964 ,0.912 0 ,3776 ,127 ,4096 ,0 ,0 ,107.135 ,107.618 ,0.996 0 ,3808 ,127 ,4096 ,0 ,0 ,106.308 ,106.252 ,1.001 0 ,384 ,127 ,128 ,0 ,0 ,7.067 ,7.368 ,0.959 0 ,384 ,127 ,256 ,0 ,0 ,12.939 ,13.235 ,0.978 0 ,384 ,127 ,512 ,0 ,0 ,15.149 ,15.802 ,0.959 0 ,384 ,127 ,64 ,0 ,0 ,5.521 ,6.014 ,0.918 0 ,3840 ,127 ,4096 ,0 ,0 ,109.957 ,107.854 ,1.019 0 ,3872 ,127 ,4096 ,0 ,0 ,110.377 ,109.542 ,1.008 0 ,3904 ,127 ,4096 ,0 ,0 ,109.019 ,108.598 ,1.004 0 ,3936 ,127 ,4096 ,0 ,0 ,110.068 ,109.132 ,1.009 0 ,3968 ,127 ,4096 ,0 ,0 ,114.341 ,112.557 ,1.016 0 ,4 ,127 ,3 ,0 ,0 ,3.435 ,3.626 ,0.947 0 ,4 ,127 ,3 ,0 ,23 ,3.548 ,3.801 ,0.933 0 ,4000 ,127 ,4096 ,0 ,0 ,113.432 ,112.38 ,1.009 0 ,4032 ,127 ,4096 ,0 ,0 ,111.913 ,112.306 ,0.996 0 ,4064 ,127 ,4096 ,0 ,0 ,112.393 ,111.56 ,1.007 0 ,4096 ,127 ,1024 ,0 ,0 ,28.261 ,28.808 ,0.981 0 ,4096 ,127 ,1024 ,0 ,23 ,28.045 ,28.644 ,0.979 0 ,4096 ,127 ,128 ,0 ,0 ,7.124 ,7.351 ,0.969 0 ,4096 ,127 ,128 ,0 ,23 ,7.016 ,7.395 ,0.949 0 ,4096 ,127 ,2048 ,0 ,0 ,48.17 ,48.541 ,0.992 0 ,4096 ,127 ,2048 ,0 ,23 ,48.388 ,49.056 ,0.986 0 ,4096 ,127 ,256 ,0 ,0 ,12.957 ,13.163 ,0.984 0 ,4096 ,127 ,256 ,0 ,23 ,13.13 ,13.266 ,0.99 0 ,4096 ,127 ,32 ,0 ,0 ,4.764 ,4.838 ,0.985 0 ,4096 ,127 ,32 ,0 ,23 ,4.754 ,4.723 ,1.006 0 ,4096 ,127 ,3776 ,0 ,0 ,106.852 ,106.349 ,1.005 0 ,4096 ,127 ,3808 ,0 ,0 ,106.998 ,106.658 ,1.003 0 ,4096 ,127 ,3840 ,0 ,0 ,110.603 ,107.567 ,1.028 0 ,4096 ,127 ,3872 ,0 ,0 ,110.267 ,108.296 ,1.018 0 ,4096 ,127 ,3904 ,0 ,0 ,109.43 ,109.724 ,0.997 0 ,4096 ,127 ,3936 ,0 ,0 ,108.706 ,111.21 ,0.977 0 ,4096 ,127 ,3968 ,0 ,0 ,110.841 ,112.385 ,0.986 0 ,4096 ,127 ,4000 ,0 ,0 ,113.403 ,111.569 ,1.016 0 ,4096 ,127 ,4032 ,0 ,0 ,111.23 ,111.98 ,0.993 0 ,4096 ,127 ,4064 ,0 ,0 ,112.755 ,112.228 ,1.005 0 ,4096 ,127 ,4128 ,0 ,0 ,115.807 ,113.662 ,1.019 0 ,4096 ,127 ,4160 ,0 ,0 ,114.45 ,113.133 ,1.012 0 ,4096 ,127 ,4192 ,0 ,0 ,115.81 ,113.153 ,1.023 0 ,4096 ,127 ,4224 ,0 ,0 ,113.306 ,113.886 ,0.995 0 ,4096 ,127 ,4256 ,0 ,0 ,115.746 ,113.454 ,1.02 0 ,4096 ,127 ,4288 ,0 ,0 ,115.042 ,114.579 ,1.004 0 ,4096 ,127 ,4320 ,0 ,0 ,116.733 ,113.221 ,1.031 0 ,4096 ,127 ,4352 ,0 ,0 ,114.863 ,113.593 ,1.011 0 ,4096 ,127 ,4384 ,0 ,0 ,116.745 ,113.405 ,1.029 0 ,4096 ,127 ,4416 ,0 ,0 ,114.161 ,113.181 ,1.009 0 ,4096 ,127 ,512 ,0 ,0 ,18.172 ,18.892 ,0.962 0 ,4096 ,127 ,512 ,0 ,23 ,19.072 ,19.144 ,0.996 0 ,4096 ,127 ,64 ,0 ,0 ,5.245 ,5.689 ,0.922 0 ,4096 ,127 ,64 ,0 ,23 ,5.296 ,5.714 ,0.927 0 ,4128 ,127 ,4096 ,0 ,0 ,115.166 ,114.833 ,1.003 0 ,416 ,127 ,128 ,0 ,0 ,7.043 ,7.394 ,0.953 0 ,416 ,127 ,256 ,0 ,0 ,13.002 ,13.18 ,0.987 0 ,416 ,127 ,512 ,0 ,0 ,16.393 ,16.776 ,0.977 0 ,4160 ,127 ,4096 ,0 ,0 ,119.857 ,115.093 ,1.041 0 ,4192 ,127 ,4096 ,0 ,0 ,114.634 ,113.745 ,1.008 0 ,4224 ,127 ,4096 ,0 ,0 ,117.198 ,113.874 ,1.029 0 ,4256 ,127 ,4096 ,0 ,0 ,115.097 ,113.647 ,1.013 0 ,4288 ,127 ,4096 ,0 ,0 ,113.484 ,114.45 ,0.992 0 ,4320 ,127 ,4096 ,0 ,0 ,115.203 ,114.171 ,1.009 0 ,4352 ,127 ,4096 ,0 ,0 ,114.364 ,113.866 ,1.004 0 ,4384 ,127 ,4096 ,0 ,0 ,115.509 ,114.031 ,1.013 0 ,4416 ,127 ,4096 ,0 ,0 ,118.825 ,113.969 ,1.043 0 ,448 ,127 ,128 ,0 ,0 ,7.228 ,8.146 ,0.887 0 ,448 ,127 ,256 ,0 ,0 ,12.88 ,13.158 ,0.979 0 ,448 ,127 ,512 ,0 ,0 ,19.471 ,18.169 ,1.072 0 ,48 ,127 ,16 ,0 ,0 ,3.307 ,3.81 ,0.868 0 ,480 ,127 ,256 ,0 ,0 ,12.896 ,13.087 ,0.985 0 ,480 ,127 ,512 ,0 ,0 ,18.529 ,18.077 ,1.025 0 ,5 ,127 ,4 ,0 ,0 ,3.576 ,3.67 ,0.974 0 ,5 ,127 ,4 ,0 ,23 ,3.521 ,3.827 ,0.92 0 ,512 ,127 ,192 ,0 ,0 ,12.107 ,12.181 ,0.994 0 ,512 ,127 ,224 ,0 ,0 ,12.093 ,12.201 ,0.991 0 ,512 ,127 ,256 ,0 ,0 ,12.725 ,12.987 ,0.98 0 ,512 ,127 ,256 ,0 ,23 ,13.103 ,13.716 ,0.955 0 ,512 ,127 ,288 ,0 ,0 ,13.825 ,13.897 ,0.995 0 ,512 ,127 ,320 ,0 ,0 ,15.178 ,14.967 ,1.014 0 ,512 ,127 ,352 ,0 ,0 ,15.153 ,14.971 ,1.012 0 ,512 ,127 ,384 ,0 ,0 ,15.071 ,15.901 ,0.948 0 ,512 ,127 ,416 ,0 ,0 ,16.275 ,16.735 ,0.973 0 ,512 ,127 ,448 ,0 ,0 ,18.028 ,17.982 ,1.003 0 ,512 ,127 ,480 ,0 ,0 ,18.016 ,17.867 ,1.008 0 ,512 ,127 ,544 ,0 ,0 ,18.413 ,18.819 ,0.978 0 ,512 ,127 ,576 ,0 ,0 ,18.447 ,18.844 ,0.979 0 ,512 ,127 ,608 ,0 ,0 ,18.033 ,18.876 ,0.955 0 ,512 ,127 ,640 ,0 ,0 ,18.087 ,18.878 ,0.958 0 ,512 ,127 ,672 ,0 ,0 ,18.097 ,18.809 ,0.962 0 ,512 ,127 ,704 ,0 ,0 ,18.175 ,18.882 ,0.963 0 ,512 ,127 ,736 ,0 ,0 ,18.202 ,18.79 ,0.969 0 ,512 ,127 ,768 ,0 ,0 ,18.273 ,18.979 ,0.963 0 ,512 ,127 ,800 ,0 ,0 ,18.139 ,19.157 ,0.947 0 ,512 ,127 ,832 ,0 ,0 ,18.662 ,18.941 ,0.985 0 ,544 ,127 ,256 ,0 ,0 ,12.943 ,13.125 ,0.986 0 ,544 ,127 ,512 ,0 ,0 ,18.26 ,18.993 ,0.961 0 ,576 ,127 ,256 ,0 ,0 ,12.868 ,13.241 ,0.972 0 ,576 ,127 ,512 ,0 ,0 ,18.084 ,18.759 ,0.964 0 ,6 ,127 ,5 ,0 ,0 ,3.521 ,3.83 ,0.919 0 ,6 ,127 ,5 ,0 ,23 ,3.489 ,3.808 ,0.916 0 ,608 ,127 ,512 ,0 ,0 ,18.142 ,18.837 ,0.963 0 ,64 ,127 ,128 ,0 ,0 ,5.242 ,5.718 ,0.917 0 ,64 ,127 ,160 ,0 ,0 ,5.217 ,5.694 ,0.916 0 ,64 ,127 ,192 ,0 ,0 ,5.191 ,5.697 ,0.911 0 ,64 ,127 ,224 ,0 ,0 ,5.197 ,5.691 ,0.913 0 ,64 ,127 ,256 ,0 ,0 ,5.227 ,5.723 ,0.913 0 ,64 ,127 ,288 ,0 ,0 ,5.223 ,5.685 ,0.919 0 ,64 ,127 ,32 ,0 ,0 ,4.716 ,4.683 ,1.007 0 ,64 ,127 ,320 ,0 ,0 ,5.438 ,5.91 ,0.92 0 ,64 ,127 ,352 ,0 ,0 ,5.484 ,5.959 ,0.92 0 ,64 ,127 ,384 ,0 ,0 ,5.291 ,5.742 ,0.921 0 ,64 ,127 ,96 ,0 ,0 ,5.218 ,5.718 ,0.913 0 ,640 ,127 ,512 ,0 ,0 ,18.136 ,18.77 ,0.966 0 ,672 ,127 ,512 ,0 ,0 ,18.151 ,18.806 ,0.965 0 ,7 ,127 ,6 ,0 ,0 ,3.427 ,3.828 ,0.895 0 ,7 ,127 ,6 ,0 ,23 ,3.441 ,3.864 ,0.89 0 ,704 ,127 ,1024 ,0 ,0 ,23.45 ,22.943 ,1.022 0 ,704 ,127 ,512 ,0 ,0 ,18.597 ,18.792 ,0.99 0 ,736 ,127 ,1024 ,0 ,0 ,23.884 ,22.97 ,1.04 0 ,736 ,127 ,512 ,0 ,0 ,18.207 ,18.872 ,0.965 0 ,768 ,127 ,1024 ,0 ,0 ,23.011 ,23.516 ,0.979 0 ,768 ,127 ,512 ,0 ,0 ,18.216 ,18.837 ,0.967 0 ,7872 ,127 ,8192 ,0 ,0 ,188.983 ,188.439 ,1.003 0 ,7904 ,127 ,8192 ,0 ,0 ,190.441 ,188.431 ,1.011 0 ,7936 ,127 ,8192 ,0 ,0 ,191.761 ,190.242 ,1.008 0 ,7968 ,127 ,8192 ,0 ,0 ,192.509 ,190.241 ,1.012 0 ,8 ,127 ,7 ,0 ,0 ,3.551 ,3.88 ,0.915 0 ,8 ,127 ,7 ,0 ,23 ,3.425 ,3.836 ,0.893 0 ,80 ,127 ,16 ,0 ,0 ,3.418 ,3.784 ,0.903 0 ,800 ,127 ,1024 ,0 ,0 ,24.447 ,23.902 ,1.023 0 ,800 ,127 ,512 ,0 ,0 ,18.203 ,18.902 ,0.963 0 ,8000 ,127 ,8192 ,0 ,0 ,191.608 ,189.985 ,1.009 0 ,8032 ,127 ,8192 ,0 ,0 ,190.488 ,198.673 ,0.959 0 ,8064 ,127 ,8192 ,0 ,0 ,193.941 ,192.12 ,1.009 0 ,8096 ,127 ,8192 ,0 ,0 ,195.619 ,193.212 ,1.012 0 ,8128 ,127 ,8192 ,0 ,0 ,194.105 ,193.11 ,1.005 0 ,8160 ,127 ,8192 ,0 ,0 ,194.197 ,193.289 ,1.005 0 ,832 ,127 ,1024 ,0 ,0 ,26.28 ,25.929 ,1.014 0 ,832 ,127 ,512 ,0 ,0 ,19.137 ,18.783 ,1.019 0 ,864 ,127 ,1024 ,0 ,0 ,26.167 ,25.502 ,1.026 0 ,896 ,127 ,1024 ,0 ,0 ,25.73 ,25.839 ,0.996 0 ,9 ,127 ,8 ,0 ,0 ,3.529 ,3.896 ,0.906 0 ,9 ,127 ,8 ,0 ,23 ,3.429 ,3.754 ,0.913 0 ,928 ,127 ,1024 ,0 ,0 ,27.35 ,26.841 ,1.019 0 ,96 ,127 ,128 ,0 ,0 ,5.992 ,6.295 ,0.952 0 ,96 ,127 ,256 ,0 ,0 ,6.051 ,6.24 ,0.97 0 ,96 ,127 ,32 ,0 ,0 ,4.641 ,4.757 ,0.976 0 ,96 ,127 ,64 ,0 ,0 ,5.34 ,5.683 ,0.94 0 ,960 ,127 ,1024 ,0 ,0 ,29.039 ,28.286 ,1.027 0 ,992 ,127 ,1024 ,0 ,0 ,28.868 ,28.33 ,1.019 1 ,2048 ,127 ,32 ,0 ,0 ,4.646 ,4.616 ,1.006 1 ,2048 ,127 ,32 ,0 ,23 ,4.623 ,4.581 ,1.009 1 ,256 ,127 ,64 ,0 ,0 ,5.294 ,5.771 ,0.917 1 ,256 ,127 ,64 ,0 ,23 ,5.334 ,5.759 ,0.926 1 ,4096 ,127 ,32 ,0 ,0 ,4.68 ,4.705 ,0.995 1 ,4096 ,127 ,32 ,0 ,23 ,4.711 ,4.68 ,1.007 112 ,512 ,127 ,256 ,0 ,0 ,12.16 ,12.221 ,0.995 112 ,512 ,127 ,256 ,0 ,23 ,12.168 ,12.232 ,0.995 16 ,512 ,127 ,256 ,0 ,0 ,13.435 ,13.243 ,1.015 16 ,512 ,127 ,256 ,0 ,23 ,13.59 ,13.315 ,1.021 2 ,2048 ,127 ,64 ,0 ,0 ,5.275 ,5.669 ,0.93 2 ,2048 ,127 ,64 ,0 ,23 ,5.453 ,6.489 ,0.84 2 ,256 ,127 ,64 ,0 ,0 ,5.212 ,5.665 ,0.92 2 ,256 ,127 ,64 ,0 ,23 ,5.243 ,5.709 ,0.918 2 ,4096 ,127 ,64 ,0 ,0 ,5.303 ,5.682 ,0.933 2 ,4096 ,127 ,64 ,0 ,23 ,5.222 ,5.702 ,0.916 3 ,2048 ,127 ,128 ,0 ,0 ,6.955 ,7.269 ,0.957 3 ,2048 ,127 ,128 ,0 ,23 ,7.071 ,7.28 ,0.971 3 ,256 ,127 ,64 ,0 ,0 ,5.232 ,5.698 ,0.918 3 ,256 ,127 ,64 ,0 ,23 ,5.279 ,5.701 ,0.926 3 ,4096 ,127 ,128 ,0 ,0 ,7.061 ,7.349 ,0.961 3 ,4096 ,127 ,128 ,0 ,23 ,7.077 ,7.301 ,0.969 32 ,512 ,127 ,256 ,0 ,0 ,13.98 ,13.911 ,1.005 32 ,512 ,127 ,256 ,0 ,23 ,13.886 ,13.902 ,0.999 4 ,2048 ,127 ,256 ,0 ,0 ,12.887 ,13.167 ,0.979 4 ,2048 ,127 ,256 ,0 ,23 ,12.944 ,13.153 ,0.984 4 ,256 ,127 ,64 ,0 ,0 ,5.204 ,5.683 ,0.916 4 ,256 ,127 ,64 ,0 ,23 ,5.307 ,5.74 ,0.925 4 ,4096 ,127 ,256 ,0 ,0 ,12.879 ,13.11 ,0.982 4 ,4096 ,127 ,256 ,0 ,23 ,12.951 ,13.149 ,0.985 48 ,512 ,127 ,256 ,0 ,0 ,14.086 ,14.075 ,1.001 48 ,512 ,127 ,256 ,0 ,23 ,14.025 ,14.042 ,0.999 5 ,2048 ,127 ,512 ,0 ,0 ,18.365 ,18.915 ,0.971 5 ,2048 ,127 ,512 ,0 ,23 ,18.154 ,18.828 ,0.964 5 ,256 ,127 ,64 ,0 ,0 ,5.246 ,5.696 ,0.921 5 ,256 ,127 ,64 ,0 ,23 ,5.263 ,5.676 ,0.927 5 ,4096 ,127 ,512 ,0 ,0 ,18.352 ,19.037 ,0.964 5 ,4096 ,127 ,512 ,0 ,23 ,18.16 ,18.894 ,0.961 6 ,2048 ,127 ,1024 ,0 ,0 ,28.802 ,28.303 ,1.018 6 ,2048 ,127 ,1024 ,0 ,23 ,28.685 ,27.894 ,1.028 6 ,256 ,127 ,64 ,0 ,0 ,5.21 ,5.656 ,0.921 6 ,256 ,127 ,64 ,0 ,23 ,5.301 ,5.707 ,0.929 6 ,4096 ,127 ,1024 ,0 ,0 ,27.401 ,28.065 ,0.976 6 ,4096 ,127 ,1024 ,0 ,23 ,27.327 ,27.901 ,0.979 64 ,512 ,127 ,256 ,0 ,0 ,15.265 ,15.029 ,1.016 64 ,512 ,127 ,256 ,0 ,23 ,15.297 ,15.008 ,1.019 7 ,2048 ,127 ,2048 ,0 ,0 ,48.207 ,47.941 ,1.006 7 ,2048 ,127 ,2048 ,0 ,23 ,48.017 ,48.214 ,0.996 7 ,256 ,127 ,64 ,0 ,0 ,5.219 ,5.724 ,0.912 7 ,256 ,127 ,64 ,0 ,23 ,5.24 ,5.667 ,0.925 7 ,4096 ,127 ,2048 ,0 ,0 ,48.105 ,48.19 ,0.998 7 ,4096 ,127 ,2048 ,0 ,23 ,48.277 ,48.418 ,0.997 80 ,512 ,127 ,256 ,0 ,0 ,15.197 ,14.997 ,1.013 80 ,512 ,127 ,256 ,0 ,23 ,15.449 ,15.249 ,1.013 96 ,512 ,127 ,256 ,0 ,0 ,12.192 ,12.072 ,1.01 96 ,512 ,127 ,256 ,0 ,23 ,12.349 ,12.371 ,0.998 0.9651929728891862
diff --git a/sysdeps/x86_64/multiarch/strchr-evex.S b/sysdeps/x86_64/multiarch/strchr-evex.S index a1c15c4419..c2a0d112f7 100644 --- a/sysdeps/x86_64/multiarch/strchr-evex.S +++ b/sysdeps/x86_64/multiarch/strchr-evex.S @@ -26,48 +26,75 @@ # define STRCHR __strchr_evex # endif -# define VMOVU vmovdqu64 -# define VMOVA vmovdqa64 +# ifndef VEC_SIZE +# include "x86-evex256-vecs.h" +# endif # ifdef USE_AS_WCSCHR # define VPBROADCAST vpbroadcastd -# define VPCMP vpcmpd +# define VPCMP vpcmpd +# define VPCMPEQ vpcmpeqd # define VPTESTN vptestnmd +# define VPTEST vptestmd # define VPMINU vpminud # define CHAR_REG esi -# define SHIFT_REG ecx +# define SHIFT_REG rcx # define CHAR_SIZE 4 + +# define USE_WIDE_CHAR # else # define VPBROADCAST vpbroadcastb -# define VPCMP vpcmpb +# define VPCMP vpcmpb +# define VPCMPEQ vpcmpeqb # define VPTESTN vptestnmb +# define VPTEST vptestmb # define VPMINU vpminub # define CHAR_REG sil -# define SHIFT_REG edx +# define SHIFT_REG rdi # define CHAR_SIZE 1 # endif -# define XMMZERO xmm16 - -# define YMMZERO ymm16 -# define YMM0 ymm17 -# define YMM1 ymm18 -# define YMM2 ymm19 -# define YMM3 ymm20 -# define YMM4 ymm21 -# define YMM5 ymm22 -# define YMM6 ymm23 -# define YMM7 ymm24 -# define YMM8 ymm25 - -# define VEC_SIZE 32 -# define PAGE_SIZE 4096 -# define CHAR_PER_VEC (VEC_SIZE / CHAR_SIZE) - - .section .text.evex,"ax",@progbits -ENTRY_P2ALIGN (STRCHR, 5) - /* Broadcast CHAR to YMM0. */ - VPBROADCAST %esi, %YMM0 +# include "reg-macros.h" + +# if VEC_SIZE == 64 +# define MASK_GPR rcx +# define LOOP_REG rax + +# define COND_MASK(k_reg) {%k_reg} +# else +# define MASK_GPR rax +# define LOOP_REG rdi + +# define COND_MASK(k_reg) +# endif + +# define CHAR_PER_VEC (VEC_SIZE / CHAR_SIZE) + + +# if CHAR_PER_VEC == 64 +# define LAST_VEC_OFFSET (VEC_SIZE * 3) +# define TESTZ(reg) incq %VGPR_SZ(reg, 64) +# else + +# if CHAR_PER_VEC == 32 +# define TESTZ(reg) incl %VGPR_SZ(reg, 32) +# elif CHAR_PER_VEC == 16 +# define TESTZ(reg) incw %VGPR_SZ(reg, 16) +# else +# define TESTZ(reg) incb %VGPR_SZ(reg, 8) +# endif + +# define LAST_VEC_OFFSET (VEC_SIZE * 2) +# endif + +# define VMATCH VMM(0) + +# define PAGE_SIZE 4096 + + .section SECTION(.text), "ax", @progbits +ENTRY_P2ALIGN (STRCHR, 6) + /* Broadcast CHAR to VEC_0. */ + VPBROADCAST %esi, %VMATCH movl %edi, %eax andl $(PAGE_SIZE - 1), %eax /* Check if we cross page boundary with one vector load. @@ -75,19 +102,27 @@ ENTRY_P2ALIGN (STRCHR, 5) cmpl $(PAGE_SIZE - VEC_SIZE), %eax ja L(cross_page_boundary) + /* Check the first VEC_SIZE bytes. Search for both CHAR and the null bytes. */ - VMOVU (%rdi), %YMM1 - + VMOVU (%rdi), %VMM(1) /* Leaves only CHARS matching esi as 0. */ - vpxorq %YMM1, %YMM0, %YMM2 - VPMINU %YMM2, %YMM1, %YMM2 - /* Each bit in K0 represents a CHAR or a null byte in YMM1. */ - VPTESTN %YMM2, %YMM2, %k0 - kmovd %k0, %eax - testl %eax, %eax + vpxorq %VMM(1), %VMATCH, %VMM(2) + VPMINU %VMM(2), %VMM(1), %VMM(2) + /* Each bit in K0 represents a CHAR or a null byte in VEC_1. */ + VPTESTN %VMM(2), %VMM(2), %k0 + KMOV %k0, %VRAX +# if VEC_SIZE == 64 && defined USE_AS_STRCHRNUL + /* If VEC_SIZE == 64 && STRCHRNUL use bsf to test condition so + that all logic for match/null in first VEC first in 1x cache + lines. This has a slight cost to larger sizes. */ + bsf %VRAX, %VRAX + jz L(aligned_more) +# else + test %VRAX, %VRAX jz L(aligned_more) - tzcntl %eax, %eax + bsf %VRAX, %VRAX +# endif # ifndef USE_AS_STRCHRNUL /* Found CHAR or the null byte. */ cmp (%rdi, %rax, CHAR_SIZE), %CHAR_REG @@ -109,287 +144,374 @@ ENTRY_P2ALIGN (STRCHR, 5) # endif ret - - - .p2align 4,, 10 -L(first_vec_x4): -# ifndef USE_AS_STRCHRNUL - /* Check to see if first match was CHAR (k0) or null (k1). */ - kmovd %k0, %eax - tzcntl %eax, %eax - kmovd %k1, %ecx - /* bzhil will not be 0 if first match was null. */ - bzhil %eax, %ecx, %ecx - jne L(zero) -# else - /* Combine CHAR and null matches. */ - kord %k0, %k1, %k0 - kmovd %k0, %eax - tzcntl %eax, %eax -# endif - /* NB: Multiply sizeof char type (1 or 4) to get the number of - bytes. */ - leaq (VEC_SIZE * 4)(%rdi, %rax, CHAR_SIZE), %rax - ret - # ifndef USE_AS_STRCHRNUL L(zero): xorl %eax, %eax ret # endif - - .p2align 4 + .p2align 4,, 2 +L(first_vec_x3): + subq $-(VEC_SIZE * 2), %rdi +# if VEC_SIZE == 32 + /* Reuse L(first_vec_x3) for last VEC2 only for VEC_SIZE == 32. + For VEC_SIZE == 64 the registers don't match. */ +L(last_vec_x2): +# endif L(first_vec_x1): /* Use bsf here to save 1-byte keeping keeping the block in 1x fetch block. eax guranteed non-zero. */ - bsfl %eax, %eax + bsf %VRCX, %VRCX # ifndef USE_AS_STRCHRNUL - /* Found CHAR or the null byte. */ - cmp (VEC_SIZE)(%rdi, %rax, CHAR_SIZE), %CHAR_REG + /* Found CHAR or the null byte. */ + cmp (VEC_SIZE)(%rdi, %rcx, CHAR_SIZE), %CHAR_REG jne L(zero) - # endif /* NB: Multiply sizeof char type (1 or 4) to get the number of bytes. */ - leaq (VEC_SIZE)(%rdi, %rax, CHAR_SIZE), %rax + leaq (VEC_SIZE)(%rdi, %rcx, CHAR_SIZE), %rax ret - .p2align 4,, 10 + .p2align 4,, 2 +L(first_vec_x4): + subq $-(VEC_SIZE * 2), %rdi L(first_vec_x2): # ifndef USE_AS_STRCHRNUL /* Check to see if first match was CHAR (k0) or null (k1). */ - kmovd %k0, %eax - tzcntl %eax, %eax - kmovd %k1, %ecx + KMOV %k0, %VRAX + tzcnt %VRAX, %VRAX + KMOV %k1, %VRCX /* bzhil will not be 0 if first match was null. */ - bzhil %eax, %ecx, %ecx + bzhi %VRAX, %VRCX, %VRCX jne L(zero) # else /* Combine CHAR and null matches. */ - kord %k0, %k1, %k0 - kmovd %k0, %eax - tzcntl %eax, %eax + KOR %k0, %k1, %k0 + KMOV %k0, %VRAX + bsf %VRAX, %VRAX # endif /* NB: Multiply sizeof char type (1 or 4) to get the number of bytes. */ leaq (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %rax ret - .p2align 4,, 10 -L(first_vec_x3): - /* Use bsf here to save 1-byte keeping keeping the block in 1x - fetch block. eax guranteed non-zero. */ - bsfl %eax, %eax -# ifndef USE_AS_STRCHRNUL - /* Found CHAR or the null byte. */ - cmp (VEC_SIZE * 3)(%rdi, %rax, CHAR_SIZE), %CHAR_REG - jne L(zero) +# ifdef USE_AS_STRCHRNUL + /* We use this as a hook to get imm8 encoding for the jmp to + L(page_cross_boundary). This allows the hot case of a + match/null-term in first VEC to fit entirely in 1 cache + line. */ +L(cross_page_boundary): + jmp L(cross_page_boundary_real) # endif - /* NB: Multiply sizeof char type (1 or 4) to get the number of - bytes. */ - leaq (VEC_SIZE * 3)(%rdi, %rax, CHAR_SIZE), %rax - ret .p2align 4 L(aligned_more): +L(cross_page_continue): /* Align data to VEC_SIZE. */ andq $-VEC_SIZE, %rdi -L(cross_page_continue): - /* Check the next 4 * VEC_SIZE. Only one VEC_SIZE at a time since - data is only aligned to VEC_SIZE. Use two alternating methods - for checking VEC to balance latency and port contention. */ - /* This method has higher latency but has better port - distribution. */ - VMOVA (VEC_SIZE)(%rdi), %YMM1 + /* Check the next 4 * VEC_SIZE. Only one VEC_SIZE at a time + since data is only aligned to VEC_SIZE. Use two alternating + methods for checking VEC to balance latency and port + contention. */ + + /* Method(1) with 8c latency: + For VEC_SIZE == 32: + p0 * 1.83, p1 * 0.83, p5 * 1.33 + For VEC_SIZE == 64: + p0 * 2.50, p1 * 0.00, p5 * 1.50 */ + VMOVA (VEC_SIZE)(%rdi), %VMM(1) /* Leaves only CHARS matching esi as 0. */ - vpxorq %YMM1, %YMM0, %YMM2 - VPMINU %YMM2, %YMM1, %YMM2 - /* Each bit in K0 represents a CHAR or a null byte in YMM1. */ - VPTESTN %YMM2, %YMM2, %k0 - kmovd %k0, %eax - testl %eax, %eax + vpxorq %VMM(1), %VMATCH, %VMM(2) + VPMINU %VMM(2), %VMM(1), %VMM(2) + /* Each bit in K0 represents a CHAR or a null byte in VEC_1. */ + VPTESTN %VMM(2), %VMM(2), %k0 + KMOV %k0, %VRCX + test %VRCX, %VRCX jnz L(first_vec_x1) - /* This method has higher latency but has better port - distribution. */ - VMOVA (VEC_SIZE * 2)(%rdi), %YMM1 - /* Each bit in K0 represents a CHAR in YMM1. */ - VPCMP $0, %YMM1, %YMM0, %k0 - /* Each bit in K1 represents a CHAR in YMM1. */ - VPTESTN %YMM1, %YMM1, %k1 - kortestd %k0, %k1 + /* Method(2) with 6c latency: + For VEC_SIZE == 32: + p0 * 1.00, p1 * 0.00, p5 * 2.00 + For VEC_SIZE == 64: + p0 * 1.00, p1 * 0.00, p5 * 2.00 */ + VMOVA (VEC_SIZE * 2)(%rdi), %VMM(1) + /* Each bit in K0 represents a CHAR in VEC_1. */ + VPCMPEQ %VMM(1), %VMATCH, %k0 + /* Each bit in K1 represents a CHAR in VEC_1. */ + VPTESTN %VMM(1), %VMM(1), %k1 + KORTEST %k0, %k1 jnz L(first_vec_x2) - VMOVA (VEC_SIZE * 3)(%rdi), %YMM1 + /* By swapping between Method 1/2 we get more fair port + distrubition and better throughput. */ + + VMOVA (VEC_SIZE * 3)(%rdi), %VMM(1) /* Leaves only CHARS matching esi as 0. */ - vpxorq %YMM1, %YMM0, %YMM2 - VPMINU %YMM2, %YMM1, %YMM2 - /* Each bit in K0 represents a CHAR or a null byte in YMM1. */ - VPTESTN %YMM2, %YMM2, %k0 - kmovd %k0, %eax - testl %eax, %eax + vpxorq %VMM(1), %VMATCH, %VMM(2) + VPMINU %VMM(2), %VMM(1), %VMM(2) + /* Each bit in K0 represents a CHAR or a null byte in VEC_1. */ + VPTESTN %VMM(2), %VMM(2), %k0 + KMOV %k0, %VRCX + test %VRCX, %VRCX jnz L(first_vec_x3) - VMOVA (VEC_SIZE * 4)(%rdi), %YMM1 - /* Each bit in K0 represents a CHAR in YMM1. */ - VPCMP $0, %YMM1, %YMM0, %k0 - /* Each bit in K1 represents a CHAR in YMM1. */ - VPTESTN %YMM1, %YMM1, %k1 - kortestd %k0, %k1 + VMOVA (VEC_SIZE * 4)(%rdi), %VMM(1) + /* Each bit in K0 represents a CHAR in VEC_1. */ + VPCMPEQ %VMM(1), %VMATCH, %k0 + /* Each bit in K1 represents a CHAR in VEC_1. */ + VPTESTN %VMM(1), %VMM(1), %k1 + KORTEST %k0, %k1 jnz L(first_vec_x4) /* Align data to VEC_SIZE * 4 for the loop. */ +# if VEC_SIZE == 64 + /* Use rax for the loop reg as it allows to the loop to fit in + exactly 2-cache-lines. (more efficient imm32 + gpr + encoding). */ + leaq (VEC_SIZE)(%rdi), %rax + /* No partial register stalls on evex512 processors. */ + xorb %al, %al +# else + /* For VEC_SIZE == 32 continue using rdi for loop reg so we can + reuse more code and save space. */ addq $VEC_SIZE, %rdi andq $-(VEC_SIZE * 4), %rdi - +# endif .p2align 4 L(loop_4x_vec): - /* Check 4x VEC at a time. No penalty to imm32 offset with evex - encoding. */ - VMOVA (VEC_SIZE * 4)(%rdi), %YMM1 - VMOVA (VEC_SIZE * 5)(%rdi), %YMM2 - VMOVA (VEC_SIZE * 6)(%rdi), %YMM3 - VMOVA (VEC_SIZE * 7)(%rdi), %YMM4 - - /* For YMM1 and YMM3 use xor to set the CHARs matching esi to + /* Check 4x VEC at a time. No penalty for imm32 offset with evex + encoding (if offset % VEC_SIZE == 0). */ + VMOVA (VEC_SIZE * 4)(%LOOP_REG), %VMM(1) + VMOVA (VEC_SIZE * 5)(%LOOP_REG), %VMM(2) + VMOVA (VEC_SIZE * 6)(%LOOP_REG), %VMM(3) + VMOVA (VEC_SIZE * 7)(%LOOP_REG), %VMM(4) + + /* Collect bits where VEC_1 does NOT match esi. This is later + use to mask of results (getting not matches allows us to + save an instruction on combining). */ + VPCMP $4, %VMATCH, %VMM(1), %k1 + + /* Two methods for loop depending on VEC_SIZE. This is because + with zmm registers VPMINU can only run on p0 (as opposed to + p0/p1 for ymm) so it is less prefered. */ +# if VEC_SIZE == 32 + /* For VEC_2 and VEC_3 use xor to set the CHARs matching esi to zero. */ - vpxorq %YMM1, %YMM0, %YMM5 - /* For YMM2 and YMM4 cmp not equals to CHAR and store result in - k register. Its possible to save either 1 or 2 instructions - using cmp no equals method for either YMM1 or YMM1 and YMM3 - respectively but bottleneck on p5 makes it not worth it. */ - VPCMP $4, %YMM0, %YMM2, %k2 - vpxorq %YMM3, %YMM0, %YMM7 - VPCMP $4, %YMM0, %YMM4, %k4 - - /* Use min to select all zeros from either xor or end of string). - */ - VPMINU %YMM1, %YMM5, %YMM1 - VPMINU %YMM3, %YMM7, %YMM3 + vpxorq %VMM(2), %VMATCH, %VMM(6) + vpxorq %VMM(3), %VMATCH, %VMM(7) - /* Use min + zeromask to select for zeros. Since k2 and k4 will - have 0 as positions that matched with CHAR which will set - zero in the corresponding destination bytes in YMM2 / YMM4. - */ - VPMINU %YMM1, %YMM2, %YMM2{%k2}{z} - VPMINU %YMM3, %YMM4, %YMM4 - VPMINU %YMM2, %YMM4, %YMM4{%k4}{z} - - VPTESTN %YMM4, %YMM4, %k1 - kmovd %k1, %ecx - subq $-(VEC_SIZE * 4), %rdi - testl %ecx, %ecx + /* Find non-matches in VEC_4 while combining with non-matches + from VEC_1. NB: Try and use masked predicate execution on + instructions that have mask result as it has no latency + penalty. */ + VPCMP $4, %VMATCH, %VMM(4), %k4{%k1} + + /* Combined zeros from VEC_1 / VEC_2 (search for null term). */ + VPMINU %VMM(1), %VMM(2), %VMM(2) + + /* Use min to select all zeros from either xor or end of + string). */ + VPMINU %VMM(3), %VMM(7), %VMM(3) + VPMINU %VMM(2), %VMM(6), %VMM(2) + + /* Combined zeros from VEC_2 / VEC_3 (search for null term). */ + VPMINU %VMM(3), %VMM(4), %VMM(4) + + /* Combined zeros from VEC_2 / VEC_4 (this has all null term and + esi matches for VEC_2 / VEC_3). */ + VPMINU %VMM(2), %VMM(4), %VMM(4) +# else + /* Collect non-matches for VEC_2. */ + VPCMP $4, %VMM(2), %VMATCH, %k2 + + /* Combined zeros from VEC_1 / VEC_2 (search for null term). */ + VPMINU %VMM(1), %VMM(2), %VMM(2) + + /* Find non-matches in VEC_3/VEC_4 while combining with non- + matches from VEC_1/VEC_2 respectively. */ + VPCMP $4, %VMM(3), %VMATCH, %k3{%k1} + VPCMP $4, %VMM(4), %VMATCH, %k4{%k2} + + /* Finish combining zeros in all VECs. */ + VPMINU %VMM(3), %VMM(4), %VMM(4) + + /* Combine in esi matches for VEC_3 (if there was a match with + esi, the corresponding bit in %k3 is zero so the + VPMINU_MASKZ will have a zero in the result). NB: This make + the VPMINU 3c latency. The only way to avoid it is to + createa a 12c dependency chain on all the `VPCMP $4, ...` + which has higher total latency. */ + VPMINU %VMM(2), %VMM(4), %VMM(4){%k3}{z} +# endif + VPTEST %VMM(4), %VMM(4), %k0{%k4} + KMOV %k0, %VRDX + subq $-(VEC_SIZE * 4), %LOOP_REG + + /* TESTZ is inc using the proper register width depending on + CHAR_PER_VEC. An esi match or null-term match leaves a zero- + bit in rdx so inc won't overflow and won't be zero. */ + TESTZ (rdx) jz L(loop_4x_vec) - VPTESTN %YMM1, %YMM1, %k0 - kmovd %k0, %eax - testl %eax, %eax - jnz L(last_vec_x1) + VPTEST %VMM(1), %VMM(1), %k0{%k1} + KMOV %k0, %VGPR(MASK_GPR) + TESTZ (MASK_GPR) +# if VEC_SIZE == 32 + /* We can reuse the return code in page_cross logic for VEC_SIZE + == 32. */ + jnz L(last_vec_x1_vec_size32) +# else + jnz L(last_vec_x1_vec_size64) +# endif + - VPTESTN %YMM2, %YMM2, %k0 - kmovd %k0, %eax - testl %eax, %eax + /* COND_MASK integates the esi matches for VEC_SIZE == 64. For + VEC_SIZE == 32 they are already integrated. */ + VPTEST %VMM(2), %VMM(2), %k0 COND_MASK(k2) + KMOV %k0, %VRCX + TESTZ (rcx) jnz L(last_vec_x2) - VPTESTN %YMM3, %YMM3, %k0 - kmovd %k0, %eax - /* Combine YMM3 matches (eax) with YMM4 matches (ecx). */ -# ifdef USE_AS_WCSCHR - sall $8, %ecx - orl %ecx, %eax - bsfl %eax, %eax + VPTEST %VMM(3), %VMM(3), %k0 COND_MASK(k3) + KMOV %k0, %VRCX +# if CHAR_PER_VEC == 64 + TESTZ (rcx) + jnz L(last_vec_x3) # else - salq $32, %rcx - orq %rcx, %rax - bsfq %rax, %rax + salq $CHAR_PER_VEC, %rdx + TESTZ (rcx) + orq %rcx, %rdx # endif + + bsfq %rdx, %rdx + # ifndef USE_AS_STRCHRNUL /* Check if match was CHAR or null. */ - cmp (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %CHAR_REG + cmp (LAST_VEC_OFFSET)(%LOOP_REG, %rdx, CHAR_SIZE), %CHAR_REG jne L(zero_end) # endif /* NB: Multiply sizeof char type (1 or 4) to get the number of bytes. */ - leaq (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %rax + leaq (LAST_VEC_OFFSET)(%LOOP_REG, %rdx, CHAR_SIZE), %rax ret - .p2align 4,, 8 -L(last_vec_x1): - bsfl %eax, %eax -# ifdef USE_AS_WCSCHR - /* NB: Multiply wchar_t count by 4 to get the number of bytes. - */ - leaq (%rdi, %rax, CHAR_SIZE), %rax -# else - addq %rdi, %rax +# ifndef USE_AS_STRCHRNUL +L(zero_end): + xorl %eax, %eax + ret # endif -# ifndef USE_AS_STRCHRNUL + + /* Seperate return label for last VEC1 because for VEC_SIZE == + 32 we can reuse return code in L(page_cross) but VEC_SIZE == + 64 has mismatched registers. */ +# if VEC_SIZE == 64 + .p2align 4,, 8 +L(last_vec_x1_vec_size64): + bsf %VRCX, %VRCX +# ifndef USE_AS_STRCHRNUL /* Check if match was null. */ - cmp (%rax), %CHAR_REG + cmp (%rax, %rcx, CHAR_SIZE), %CHAR_REG jne L(zero_end) -# endif - +# endif +# ifdef USE_AS_WCSCHR + /* NB: Multiply wchar_t count by 4 to get the number of bytes. + */ + leaq (%rax, %rcx, CHAR_SIZE), %rax +# else + addq %rcx, %rax +# endif ret + /* Since we can't combine the last 2x matches for CHAR_PER_VEC + == 64 we need return label for last VEC3. */ +# if CHAR_PER_VEC == 64 .p2align 4,, 8 +L(last_vec_x3): + addq $VEC_SIZE, %LOOP_REG +# endif + + /* Duplicate L(last_vec_x2) for VEC_SIZE == 64 because we can't + reuse L(first_vec_x3) due to register mismatch. */ L(last_vec_x2): - bsfl %eax, %eax -# ifndef USE_AS_STRCHRNUL + bsf %VGPR(MASK_GPR), %VGPR(MASK_GPR) +# ifndef USE_AS_STRCHRNUL /* Check if match was null. */ - cmp (VEC_SIZE)(%rdi, %rax, CHAR_SIZE), %CHAR_REG + cmp (VEC_SIZE * 1)(%LOOP_REG, %MASK_GPR, CHAR_SIZE), %CHAR_REG jne L(zero_end) -# endif +# endif /* NB: Multiply sizeof char type (1 or 4) to get the number of bytes. */ - leaq (VEC_SIZE)(%rdi, %rax, CHAR_SIZE), %rax + leaq (VEC_SIZE * 1)(%LOOP_REG, %MASK_GPR, CHAR_SIZE), %rax ret +# endif - /* Cold case for crossing page with first load. */ - .p2align 4,, 8 + /* Cold case for crossing page with first load. */ + .p2align 4,, 10 +# ifndef USE_AS_STRCHRNUL L(cross_page_boundary): - movq %rdi, %rdx +# endif +L(cross_page_boundary_real): /* Align rdi. */ - andq $-VEC_SIZE, %rdi - VMOVA (%rdi), %YMM1 - /* Leaves only CHARS matching esi as 0. */ - vpxorq %YMM1, %YMM0, %YMM2 - VPMINU %YMM2, %YMM1, %YMM2 - /* Each bit in K0 represents a CHAR or a null byte in YMM1. */ - VPTESTN %YMM2, %YMM2, %k0 - kmovd %k0, %eax + xorq %rdi, %rax + VMOVA (PAGE_SIZE - VEC_SIZE)(%rax), %VMM(1) + /* Use high latency method of getting matches to save code size. + */ + + /* K1 has 1s where VEC(1) does NOT match esi. */ + VPCMP $4, %VMM(1), %VMATCH, %k1 + /* K0 has ones where K1 is 1 (non-match with esi), and non-zero + (null). */ + VPTEST %VMM(1), %VMM(1), %k0{%k1} + KMOV %k0, %VRAX /* Remove the leading bits. */ # ifdef USE_AS_WCSCHR - movl %edx, %SHIFT_REG + movl %edi, %VGPR_SZ(SHIFT_REG, 32) /* NB: Divide shift count by 4 since each bit in K1 represent 4 bytes. */ - sarl $2, %SHIFT_REG - andl $(CHAR_PER_VEC - 1), %SHIFT_REG + sarl $2, %VGPR_SZ(SHIFT_REG, 32) + andl $(CHAR_PER_VEC - 1), %VGPR_SZ(SHIFT_REG, 32) + + /* if wcsrchr we need to reverse matches as we can't rely on + signed shift to bring in ones. There is not sarx for + gpr8/16. Also not we can't use inc here as the lower bits + represent matches out of range so we can't rely on overflow. + */ + xorl $((1 << CHAR_PER_VEC)- 1), %eax +# endif + /* Use arithmatic shift so that leading 1s are filled in. */ + sarx %VGPR(SHIFT_REG), %VRAX, %VRAX + /* If eax is all ones then no matches for esi or NULL. */ + +# ifdef USE_AS_WCSCHR + test %VRAX, %VRAX +# else + inc %VRAX # endif - sarxl %SHIFT_REG, %eax, %eax - /* If eax is zero continue. */ - testl %eax, %eax jz L(cross_page_continue) - bsfl %eax, %eax + .p2align 4,, 10 +L(last_vec_x1_vec_size32): + bsf %VRAX, %VRAX # ifdef USE_AS_WCSCHR - /* NB: Multiply wchar_t count by 4 to get the number of - bytes. */ - leaq (%rdx, %rax, CHAR_SIZE), %rax + /* NB: Multiply wchar_t count by 4 to get the number of bytes. + */ + leaq (%rdi, %rax, CHAR_SIZE), %rax # else - addq %rdx, %rax + addq %rdi, %rax # endif # ifndef USE_AS_STRCHRNUL /* Check to see if match was CHAR or null. */ cmp (%rax), %CHAR_REG - je L(cross_page_ret) -L(zero_end): - xorl %eax, %eax -L(cross_page_ret): + jne L(zero_end_0) # endif ret +# ifndef USE_AS_STRCHRNUL +L(zero_end_0): + xorl %eax, %eax + ret +# endif END (STRCHR) #endif
Size Optimizations: 1. Condence hot path for better cache-locality. - This is most impact for strchrnul where the logic strings with len <= VEC_SIZE or with a match in the first VEC no fits entirely in the first cache line. 2. Reuse common targets in first 4x VEC and after the loop. 3. Don't align targets so aggressively if it doesn't change the number of fetch blocks it will require and put more care in avoiding the case where targets unnecessarily split cache lines. 4. Align the loop better for DSB/LSD 5. Use more code-size efficient instructions. - tzcnt ... -> bsf ... - vpcmpb $0 ... -> vpcmpeq ... 6. Align labels less aggressively, especially if it doesn't save fetch blocks / causes the basic-block to span extra cache-lines. Code Size Changes: strchr-evex.S : -63 bytes strchrnul-evex.S: -48 bytes Net perf changes: Reported as geometric mean of all improvements / regressions from N=10 runs of the benchtests. Value as New Time / Old Time so < 1.0 is improvement and 1.0 is regression. strchr-evex.S (Fixed) : 0.971 strchr-evex.S (Rand) : 0.932 strchrnul-evex.S : 0.965 Full results attached in email. Full check passes on x86-64. --- sysdeps/x86_64/multiarch/strchr-evex.S | 558 +++++++++++++++---------- 1 file changed, 340 insertions(+), 218 deletions(-)