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[74.64.106.10]) by smtp.gmail.com with ESMTPSA id t18-20020a05622a181200b0035cf5edefa6sm4882137qtc.56.2022.09.28.20.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 20:14:56 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v1 2/4] nptl: Continue use arch prefered atomic exchange in spinlock loop Date: Wed, 28 Sep 2022 20:14:52 -0700 Message-Id: <20220929031452.2551219-2-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220929031452.2551219-1-goldstein.w.n@gmail.com> References: <20220929031452.2551219-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org Sender: "Libc-alpha" Despite using the preferred atomic exchange in the initial check, the loop was unconditionally using CAS which is not desired on some architectures (those that didn't set `ATOMIC_EXCHANGE_USES_CAS`). No meaningful perf changes measured on broadwell but still seems like a reasonable change. Full check passes on x86-64. --- nptl/pthread_spin_lock.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c index 19d1759f9a..1bdd6e2048 100644 --- a/nptl/pthread_spin_lock.c +++ b/nptl/pthread_spin_lock.c @@ -20,6 +20,20 @@ #include "pthreadP.h" #include +#if ATOMIC_EXCHANGE_USES_CAS +/* Try to acquire the lock with a CAS instruction as this architecture + has no exchange instruction. The acquisition succeeds if the lock is not + acquired. */ +# define pthread_spin_lock_grab_lock(mem, val, c) \ + atomic_compare_exchange_weak_acquire (lock, &val, 1)) +#else +/* Try to acquire the lock with an exchange instruction as this architecture + has such an instruction and we assume it is faster than a CAS. + The acquisition succeeds if the lock is not in an acquired state. */ +# define pthread_spin_lock_grab_lock(mem, val, c) \ + (atomic_exchange_acquire (lock, 1) == 0) +#endif + int __pthread_spin_lock (pthread_spinlock_t *lock) { @@ -36,19 +50,8 @@ __pthread_spin_lock (pthread_spinlock_t *lock) We use acquire MO to synchronize-with the release MO store in pthread_spin_unlock, and thus ensure that prior critical sections happen-before this critical section. */ -#if ! ATOMIC_EXCHANGE_USES_CAS - /* Try to acquire the lock with an exchange instruction as this architecture - has such an instruction and we assume it is faster than a CAS. - The acquisition succeeds if the lock is not in an acquired state. */ - if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0)) + if (__glibc_likely (pthread_spin_lock_grab_lock (lock, &val, 1))) return 0; -#else - /* Try to acquire the lock with a CAS instruction as this architecture - has no exchange instruction. The acquisition succeeds if the lock is not - acquired. */ - if (__glibc_likely (atomic_compare_exchange_weak_acquire (lock, &val, 1))) - return 0; -#endif do { @@ -75,7 +78,7 @@ __pthread_spin_lock (pthread_spinlock_t *lock) /* We need acquire memory order here for the same reason as mentioned for the first try to lock the spinlock. */ } - while (!atomic_compare_exchange_weak_acquire (lock, &val, 1)); + while (!pthread_spin_lock_grab_lock (lock, &val, 1)); return 0; }