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[v5,1/2] x86: Add comment explaining no Slow_SSE4_2 check in ifunc-sse4_2

Message ID 20220630031039.3693951-1-goldstein.w.n@gmail.com
State New
Headers show
Series [v5,1/2] x86: Add comment explaining no Slow_SSE4_2 check in ifunc-sse4_2 | expand

Commit Message

Noah Goldstein June 30, 2022, 3:10 a.m. UTC 
Just for clarities sake and so that if a future implementation is
added we remember to add the check.
---
 sysdeps/x86_64/multiarch/ifunc-sse4_2.h | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
index ee36525bcf..4eb9cca7f0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
+++ b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
@@ -27,6 +27,10 @@  IFUNC_SELECTOR (void)
 {
   const struct cpu_features* cpu_features = __get_cpu_features ();
 
+  /* This function uses slow sse4.2 instructions (pcmpstri) but since
+     there is no other optimized implementation keep using.  If an
+     optimized fallback is added add a X86_ISA_CPU_FEATURE_ARCH_P
+     (cpu_features, Slow_SSE4_2) check.  */
   if (CPU_FEATURE_USABLE_P (cpu_features, SSE4_2))
     return OPTIMIZE (sse42);