From patchwork Sat Jan 15 10:13:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 1580334 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=aurel32.net header.i=@aurel32.net header.a=rsa-sha256 header.s=202004.hall header.b=Mks5X4RA; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JbYsl3TKqz9t0k for ; Sat, 15 Jan 2022 21:13:47 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CC8643857C6F for ; Sat, 15 Jan 2022 10:13:44 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by sourceware.org (Postfix) with ESMTPS id 6411A3858D35 for ; Sat, 15 Jan 2022 10:13:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6411A3858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=aurel32.net Authentication-Results: sourceware.org; spf=none smtp.mailfrom=aurel32.net DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:Message-Id:Date: Subject:Cc:To:From:Content-Type:From:Reply-To:Subject:Content-ID: Content-Description:In-Reply-To:References:X-Debbugs-Cc; bh=dXaz4JxAC8lU01lYhTuBESTJ4+tQEaHEiYnU7HQA43U=; b=Mks5X4RAEUb1YS3H2N71KLHRzn ktCvFP+X0YkJJKiOosFHTiATHCyQkijAFDl+s9IgcL4CadTsJcNB5l3PHrAxd1pNFAUAhUwdc1hoD GD/Dlvig21x8lQ0xJLpqTpvxAB6RIxYkRLTR1jemdOn9PxcjyMBYpE/Gi5tL42A5nM+DENRxzziZ7 OMHKUztpLYc9uGlmI1kn7gj85znJozUFtMtgfs18LnwywRfUNOO3ajwL6Qeypdrlr5Q4NR6RzZ63e nfaVe+NIEEC3ufV78J1rVNljMOW9VVEnj0ZWQWPQSXpCvilToy2Z2ZgwUlXcOMxYDasu4pK/LqCrQ PpV2Lojg==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1n8g3x-008vOh-PO; Sat, 15 Jan 2022 11:13:33 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.95) (envelope-from ) id 1n8g3w-002m0b-H5; Sat, 15 Jan 2022 11:13:32 +0100 From: Aurelien Jarno To: libc-alpha@sourceware.org Subject: [PATCH] x86: use default cache size if it cannot be determined [BZ #28784] Date: Sat, 15 Jan 2022 11:13:27 +0100 Message-Id: <20220115101327.661190-1-aurelien@aurel32.net> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org Sender: "Libc-alpha" In some cases (e.g QEMU, non-Intel/AMD CPU) the cache information can not be retrieved and the corresponding values are set to 0. Commit 2d651eb9265d ("x86: Move x86 processor cache info to cpu_features") changed the behaviour in such case by defining the __x86_shared_cache_size and __x86_data_cache_size variables to 0 instead of using the default values. This cause an issue with the i686 SSE2 optimized bzero/routine which assumes that the cache size is at least 128 bytes, and otherwise tries to zero/set the whole address space minus 128 bytes. Fix that by restoring the original code to only update __x86_shared_cache_size and __x86_data_cache_size variables if the corresponding cache sizes are not zero. Fixes bug 28784 Fixes commit 2d651eb9265d Reviewed-by: H.J. Lu --- sysdeps/x86/cacheinfo.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h index 4f91a1e98d..65132a9d19 100644 --- a/sysdeps/x86/cacheinfo.h +++ b/sysdeps/x86/cacheinfo.h @@ -61,14 +61,20 @@ init_cacheinfo (void) long int data = cpu_features->data_cache_size; /* Round data cache size to multiple of 256 bytes. */ data = data & ~255L; - __x86_data_cache_size_half = data / 2; - __x86_data_cache_size = data; + if (data > 0) + { + __x86_data_cache_size_half = data / 2; + __x86_data_cache_size = data; + } long int shared = cpu_features->shared_cache_size; /* Round shared cache size to multiple of 256 bytes. */ shared = shared & ~255L; - __x86_shared_cache_size_half = shared / 2; - __x86_shared_cache_size = shared; + if (shared > 0) + { + __x86_shared_cache_size_half = shared / 2; + __x86_shared_cache_size = shared; + } __x86_shared_non_temporal_threshold = cpu_features->non_temporal_threshold;