| Message ID | 20220115101327.661190-1-aurelien@aurel32.net |
|---|---|
| State | New |
| Headers | show |
| Series | x86: use default cache size if it cannot be determined [BZ #28784] | expand |
On Sat, Jan 15, 2022 at 2:13 AM Aurelien Jarno <aurelien@aurel32.net> wrote: > > In some cases (e.g QEMU, non-Intel/AMD CPU) the cache information can > not be retrieved and the corresponding values are set to 0. > > Commit 2d651eb9265d ("x86: Move x86 processor cache info to > cpu_features") changed the behaviour in such case by defining the > __x86_shared_cache_size and __x86_data_cache_size variables to 0 instead > of using the default values. This cause an issue with the i686 SSE2 > optimized bzero/routine which assumes that the cache size is at least > 128 bytes, and otherwise tries to zero/set the whole address space minus > 128 bytes. > > Fix that by restoring the original code to only update > __x86_shared_cache_size and __x86_data_cache_size variables if the > corresponding cache sizes are not zero. > > Fixes bug 28784 > Fixes commit 2d651eb9265d > --- > sysdeps/x86/cacheinfo.h | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h > index 4f91a1e98d..65132a9d19 100644 > --- a/sysdeps/x86/cacheinfo.h > +++ b/sysdeps/x86/cacheinfo.h > @@ -61,14 +61,20 @@ init_cacheinfo (void) > long int data = cpu_features->data_cache_size; > /* Round data cache size to multiple of 256 bytes. */ > data = data & ~255L; > - __x86_data_cache_size_half = data / 2; > - __x86_data_cache_size = data; > + if (data > 0) > + { > + __x86_data_cache_size_half = data / 2; > + __x86_data_cache_size = data; > + } > > long int shared = cpu_features->shared_cache_size; > /* Round shared cache size to multiple of 256 bytes. */ > shared = shared & ~255L; > - __x86_shared_cache_size_half = shared / 2; > - __x86_shared_cache_size = shared; > + if (shared > 0) > + { > + __x86_shared_cache_size_half = shared / 2; > + __x86_shared_cache_size = shared; > + } > > __x86_shared_non_temporal_threshold > = cpu_features->non_temporal_threshold; > -- > 2.34.1 > LGTM. Reviewed-by: H.J. Lu <hjl.tools@gmail.com> Thanks.
diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h index 4f91a1e98d..65132a9d19 100644 --- a/sysdeps/x86/cacheinfo.h +++ b/sysdeps/x86/cacheinfo.h @@ -61,14 +61,20 @@ init_cacheinfo (void) long int data = cpu_features->data_cache_size; /* Round data cache size to multiple of 256 bytes. */ data = data & ~255L; - __x86_data_cache_size_half = data / 2; - __x86_data_cache_size = data; + if (data > 0) + { + __x86_data_cache_size_half = data / 2; + __x86_data_cache_size = data; + } long int shared = cpu_features->shared_cache_size; /* Round shared cache size to multiple of 256 bytes. */ shared = shared & ~255L; - __x86_shared_cache_size_half = shared / 2; - __x86_shared_cache_size = shared; + if (shared > 0) + { + __x86_shared_cache_size_half = shared / 2; + __x86_shared_cache_size = shared; + } __x86_shared_non_temporal_threshold = cpu_features->non_temporal_threshold;
In some cases (e.g QEMU, non-Intel/AMD CPU) the cache information can not be retrieved and the corresponding values are set to 0. Commit 2d651eb9265d ("x86: Move x86 processor cache info to cpu_features") changed the behaviour in such case by defining the __x86_shared_cache_size and __x86_data_cache_size variables to 0 instead of using the default values. This cause an issue with the i686 SSE2 optimized bzero/routine which assumes that the cache size is at least 128 bytes, and otherwise tries to zero/set the whole address space minus 128 bytes. Fix that by restoring the original code to only update __x86_shared_cache_size and __x86_data_cache_size variables if the corresponding cache sizes are not zero. Fixes bug 28784 Fixes commit 2d651eb9265d --- sysdeps/x86/cacheinfo.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)