From patchwork Mon Jun 15 14:40:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1309560 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=libc-alpha-bounces@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49lvDS6MF0z9sRh for ; Tue, 16 Jun 2020 00:42:00 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7D4C1383E818; Mon, 15 Jun 2020 14:41:32 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 6F155383F870 for ; Mon, 15 Jun 2020 14:41:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6F155383F870 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rearnsha@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 276D111FB; Mon, 15 Jun 2020 07:41:29 -0700 (PDT) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A68863F6CF; Mon, 15 Jun 2020 07:41:28 -0700 (PDT) From: Richard Earnshaw To: libc-alpha@sourceware.org Subject: [PATCH 6/7] aarch64: Add sysv specific enabling code for memory tagging Date: Mon, 15 Jun 2020 15:40:28 +0100 Message-Id: <20200615144029.19771-7-rearnsha@arm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200615144029.19771-1-rearnsha@arm.com> References: <20200615144029.19771-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-15.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Earnshaw Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" Add various defines and stubs for enabling MTE on AArch64 sysv-like systems such as Linux. The HWCAP feature bit is copied over in the same way as other feature bits. Similarly we add a new wrapper header for mman.h to define the PROT_MTE flag that can be used with mmap and related functions. We add a new field to struct cpu_features that can be used, for example, to check whether or not certain ifunc'd routines should be bound to MTE-safe versions. Finally, if we detect that MTE should be enabled (ie via the glibc tunable); we enable MTE during startup as required. --- sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h | 2 ++ sysdeps/unix/sysv/linux/aarch64/bits/mman.h | 32 +++++++++++++++++++ .../unix/sysv/linux/aarch64/cpu-features.c | 22 +++++++++++++ .../unix/sysv/linux/aarch64/cpu-features.h | 1 + 4 files changed, 57 insertions(+) create mode 100644 sysdeps/unix/sysv/linux/aarch64/bits/mman.h diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h index f52840c2c4..4092603fd7 100644 --- a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h +++ b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h @@ -54,3 +54,5 @@ #define HWCAP_SB (1 << 29) #define HWCAP_PACA (1 << 30) #define HWCAP_PACG (1UL << 31) + +#define HWCAP2_MTE (1 << 18) diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/mman.h b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h new file mode 100644 index 0000000000..fa3f3a31f4 --- /dev/null +++ b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h @@ -0,0 +1,32 @@ +/* Definitions for POSIX memory map interface. Linux/aarch64 version. + Copyright (C) 2020 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef _SYS_MMAN_H +# error "Never use directly; include instead." +#endif + +/* The following definitions basically come from the kernel headers. + But the kernel header is not namespace clean. */ + +/* Other flags. */ +#define PROT_MTE 0x20 /* Normal Tagged mapping. */ + +#include + +/* Include generic Linux declarations. */ +#include diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c index 896c588fee..a8554f3e5d 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c @@ -19,6 +19,7 @@ #include #include #include +#include #define DCZID_DZP_MASK (1 << 4) #define DCZID_BS_MASK (0xf) @@ -83,4 +84,25 @@ init_cpu_features (struct cpu_features *cpu_features) if ((dczid & DCZID_DZP_MASK) == 0) cpu_features->zva_size = 4 << (dczid & DCZID_BS_MASK); + + /* Setup memory tagging support if the HW and kernel support it, and if + the user has requested it. */ +#if HAVE_TUNABLES + int mte_state = TUNABLE_GET (glibc, memtag, enable, unsigned, 0); + cpu_features->mte_state = (GLRO (dl_hwcap2) & HWCAP2_MTE) ? mte_state : 0; +#else + cpu_features->mte_state = 0; +#endif + /* For now, disallow tag 0, so that we can clearly see when tagged + addresses are being allocated. */ + if (cpu_features->mte_state & 2) + __prctl (PR_SET_TAGGED_ADDR_CTRL, + (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC + | (0xfffe << PR_MTE_TAG_SHIFT)), + 0, 0, 0); + else if (cpu_features->mte_state) + __prctl (PR_SET_TAGGED_ADDR_CTRL, + (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_ASYNC + | (0xfffe << PR_MTE_TAG_SHIFT)), + 0, 0, 0); } diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h index 1389cea1b3..604de27c88 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h @@ -64,6 +64,7 @@ struct cpu_features { uint64_t midr_el1; unsigned zva_size; + unsigned mte_state; }; #endif /* _CPU_FEATURES_AARCH64_H */