@@ -6,6 +6,7 @@
@menu
* PowerPC:: Facilities Specific to the PowerPC Architecture
+* RISC-V:: Facilities Specific to the RISC-V Architecture
@end menu
@node PowerPC
@@ -115,3 +116,21 @@ problem-state programs. If the program priority is medium high when the time
interval expires or if an attempt is made to set the priority to medium high
when it is not allowed, the priority is set to medium.
@end deftypefun
+
+@node RISC-V
+@appendixsec RISC-V-specific Facilities
+
+Cache management facilities specific to RISC-V systems that implement the Linux
+ABI are declared in @file{sys/cachectl.h}.
+
+@deftypefun {void} __riscv_flush_icache(void *@var{start}, void *@var{end}, unsigned long int @var{flags})
+@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
+Enforce ordering between stores and instruction cache fetches. The range of
+addresses over which ordering is enforced is specified by @var{start} and
+@var{end}. The @var{flags} argument controls the extent of this ordering, with
+the default behavior (a @var{flags} value of 0) being to enforce the fence on
+all threads in the current process. Setting the
+@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing
+ordering on only the current thread is necessary. All other flag bits are
+reserved.
+@end deftypefun
I don't know if this is actually the right place to put this: it's a Linux-specific function, and while users can call it we'd really prefer they use rely on GCC to emit it when necessary from via its cache flushing intrinsics. 2018-01-13 Palmer Dabbelt <palmer@sifive.com> * manual/platform.texi: Add RISC-V documenation for __riscv_flush_icache. --- manual/platform.texi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)