From patchwork Sat Jan 24 02:56:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 432363 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C0D0D1402A6 for ; Sat, 24 Jan 2015 13:57:10 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:subject:message-id:references :mime-version:content-type:in-reply-to; q=dns; s=default; b=nH2l JJKo5HqawCUt6fTuKA/ec7UIHs7g12+VwlEXIu/7S2cufXTmb8xFeMd1kS4Kq9eE dcJGbDBExg5I1rbx1OzbRSNtISB5YCGVXWnqgxj5I3nwupsYQs2eomGfWgyj2rD7 /WLJyF1tDtFjjfgxZNtlMcbIwEP7KDM+p3w+/Wc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:subject:message-id:references :mime-version:content-type:in-reply-to; s=default; bh=YGCgnM1fRz KMavHU5odCPqU1xjY=; b=rVi8koFJfdUAYx67IwbiWd9fPF9aG3sHWaqdmEWruj ghPs4K87P+9g0sdvAoSdAXxWvvHAilPgc5Vsa5lvgVM98PfeEdw/1u06yRLyVhW4 8YlnCuxwtxXe8JDMlH5euzgIfwKqz7dCcI7IN6jSHEqVEpcxJ5boG3SvijCMZlaq k= Received: (qmail 30140 invoked by alias); 24 Jan 2015 02:57:03 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 30001 invoked by uid 89); 24 Jan 2015 02:57:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pd0-f177.google.com X-Received: by 10.70.52.161 with SMTP id u1mr16515730pdo.44.1422068214250; Fri, 23 Jan 2015 18:56:54 -0800 (PST) Date: Fri, 23 Jan 2015 18:56:52 -0800 From: "H.J. Lu" To: Carlos O'Donell , GNU C Library , David Miller , Richard Henderson , Mike Frysinger , Andreas Schwab , "Joseph S. Myers" , Kaz Kojima , Thomas Schwinge , Marcus Shawcroft , Chris Metcalf , Chung-Lin Tang , Adhemerval Zanella , Andreas Krebbel , "Senkevich, Andrew" Subject: Re: glibc 2.21 - Machine maintainers, please test your machines. Message-ID: <20150124025652.GA2823@gmail.com> References: <54C2BDD7.7000304@redhat.com> <20150124014016.GA23003@gmail.com> <20150124021010.GA25492@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20150124021010.GA25492@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) On Fri, Jan 23, 2015 at 06:10:10PM -0800, H.J. Lu wrote: > On Fri, Jan 23, 2015 at 05:40:16PM -0800, H.J. Lu wrote: > > On Fri, Jan 23, 2015 at 04:36:51PM -0800, H.J. Lu wrote: > > > On Fri, Jan 23, 2015 at 1:32 PM, Carlos O'Donell wrote: > > > > Dear Machine Maintainers, > > > > > > > > Please start testing your machines against glibc > > > > master. > > > > > > > > Please update the glibc 2.21 release page with your > > > > testing results: > > > > > > > > https://sourceware.org/glibc/wiki/Release/2.21 > > > > > > > > If nobody objects I want to cut the release as soon > > > > as we have results for all the machines. > > > > > > > > > > We need to update __init_cpu_features in > > > sysdeps/x86_64/multiarch/init-arch.c to support the current > > > Intel processors. > > > > > > Andrew, please find out the model numbers for the current > > > Ivy Bridge, Haswell, Broadwell and Silvermont server, desktop > > > and mobile processors. > > > > > > > > > > We only need to deal with Silvermont since Ivy Bridge, Haswell and > > Broadwell, which have AVX, are treated as Core i7. The new Silvermont > > model numbers are in > > > > http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf > > > > I am testing this patch and I will check it in shortly. > > > > This is what I checked in. Andrew, please check if it works on your > Silvermont machine. > > > H.J. > --- > From d37d432b715cefb695c09b41676338f25a91d30f Mon Sep 17 00:00:00 2001 > From: "H.J. Lu" > Date: Fri, 23 Jan 2015 17:27:09 -0800 > Subject: [PATCH] Treat model numbers 0x4a/0x4d as Silvermont > > * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): > Treat model numbers 0x4a/0x4d as Intel Silvermont architecture. There are more Silvermont model numbers in CHAPTER 35 MODEL-SPECIFIC REGISTERS (MSRS): http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf I checked in the enclosed patch. H.J. --- From 972af9e8ddd870cabf8aad39b28a6e352c9cc79c Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Fri, 23 Jan 2015 18:52:45 -0800 Subject: [PATCH] Also treat model numbers 0x5a/0x5d as Silvermont --- ChangeLog | 3 ++- sysdeps/x86_64/multiarch/init-arch.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/ChangeLog b/ChangeLog index c199a5d..d746e18 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,7 +1,8 @@ 2015-01-23 H.J. Lu * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): - Treat model numbers 0x4a/0x4d as Intel Silvermont architecture. + Treat model numbers 0x4a/0x4d/0x5a/0x5d as Intel Silvermont + architecture. 2015-01-23 H.J. Lu diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c index ec71918..9299360 100644 --- a/sysdeps/x86_64/multiarch/init-arch.c +++ b/sysdeps/x86_64/multiarch/init-arch.c @@ -81,6 +81,8 @@ __init_cpu_features (void) case 0x37: case 0x4a: case 0x4d: + case 0x5a: + case 0x5d: /* Unaligned load versions are faster than SSSE3 on Silvermont. */ #if index_Fast_Unaligned_Load != index_Prefer_PMINUB_for_stringop