From patchwork Thu Sep 19 19:14:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1164804 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-105271-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="PA2GEZ5V"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Z64z6ghTz9sNf for ; Fri, 20 Sep 2019 05:15:47 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=ZUBQ0tVKnUVIT2m6YchOc0Jt4ZfogZr YrhIxaU8UyqHq8+R1hbBqQpOb1RCFErmW82Syhch9csNCsA6cIlcHnBNhNLEyz9W F7TO+FndP/wnwQCseFAuqAeYAqaAdxkNuWRZ8SLsrXmjTJMpM6A87wyUfSYOM/sm sLSvpzO2uc9A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=g/2Xp3CCZzbAao+zZLMS23zQcjI=; b=PA2GE Z5VIfrwx9zlv6UpsHx8ZQrVcjOYMhM13dvMjYZVjYFWv4o2oMjsqABEHzwf3evp4 RdXGABH27HhtFZnm0W7EaAeGyM3PQmBCA3a+1vz3Y5SedBidirMl9pOFe4e1Ue3H wiGlIXGH6CeDnFCAt8IXZCiQXy5js4uv6uHRWc= Received: (qmail 66031 invoked by alias); 19 Sep 2019 19:15:40 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 65782 invoked by uid 89); 19 Sep 2019 19:15:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 7/6] [powerpc] Rename fesetenv_mode to fesetenv_control Date: Thu, 19 Sep 2019 14:14:56 -0500 Message-Id: <1568920496-26685-1-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" fesetenv_mode is used variously to write the FPSCR exception enable bits and rounding mode bits. These are referred to as the control bits in the POWER ISA. Change the name to be reflective of its current and expected use, and match up well with fegetenv_control. 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_mode): Rename to fesetenv_control. * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate rename of fesetenv_mode to fegetenv_control. * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise. * sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise. * sysdeps/powerpc/fpu/fenv_private.h (__libc_femergeenv_ppc): Likewise. (libc_feholdsetround_noex_ppc_ctx): Likewise. Reviewed-By: Paul E Murphy --- This patch should've been tacked onto the series that I just posted "[PATCH v2 0/6] Various FPSCR-related changes", thus the "7/6". :-? This is a new patch. sysdeps/powerpc/fpu/fedisblxcpt.c | 2 +- sysdeps/powerpc/fpu/feenablxcpt.c | 2 +- sysdeps/powerpc/fpu/fenv_libc.h | 2 +- sysdeps/powerpc/fpu/fenv_private.h | 4 ++-- sysdeps/powerpc/fpu/fesetmode.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c index 870cfc8..9f86c5f 100644 --- a/sysdeps/powerpc/fpu/fedisblxcpt.c +++ b/sysdeps/powerpc/fpu/fedisblxcpt.c @@ -41,7 +41,7 @@ fedisableexcept (int excepts) fe.l &= ~new; if (fe.l != curr.l) - fesetenv_mode (fe.fenv); + fesetenv_control (fe.fenv); __TEST_AND_ENTER_NON_STOP (-1ULL, fe.l); diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index 43f6482..141cfb4 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -41,7 +41,7 @@ feenableexcept (int excepts) fe.l |= new; if (fe.l != curr.l) - fesetenv_mode (fe.fenv); + fesetenv_control (fe.fenv); __TEST_AND_EXIT_NON_STOP (0ULL, fe.l); diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 231d264..ed6cfeb 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -124,7 +124,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; /* Set the last 2 nibbles of the FPSCR, which contain the exception enables and the rounding mode. 'fegetenv_control' retrieves these bits by reading the FPSCR. */ -#define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env)); +#define fesetenv_control(env) __builtin_mtfsf (0b00000011, (env)); /* This very handy macro: - Sets the rounding mode to 'round to nearest'; diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h index ade0bfa..5eedc3b 100644 --- a/sysdeps/powerpc/fpu/fenv_private.h +++ b/sysdeps/powerpc/fpu/fenv_private.h @@ -61,7 +61,7 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask, == (FPSCR_CONTROL_MASK|FPSCR_EXCEPTIONS_MASK) && (old.l & FPSCR_EXCEPTIONS_MASK) == (new.l & FPSCR_EXCEPTIONS_MASK)) { - fesetenv_mode (new.fenv); + fesetenv_control (new.fenv); } else /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ @@ -142,7 +142,7 @@ libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r) if (__glibc_unlikely (new.l != old.l)) { __TEST_AND_ENTER_NON_STOP (old.l, 0ULL); - fesetenv_mode (new.fenv); + fesetenv_control (new.fenv); ctx->updated_status = true; } else diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c index 1e9a874..a7ead9f 100644 --- a/sysdeps/powerpc/fpu/fesetmode.c +++ b/sysdeps/powerpc/fpu/fesetmode.c @@ -36,6 +36,6 @@ fesetmode (const femode_t *modep) __TEST_AND_EXIT_NON_STOP (old.l, new.l); __TEST_AND_ENTER_NON_STOP (old.l, new.l); - fesetenv_mode (new.fenv); + fesetenv_control (new.fenv); return 0; }