From patchwork Wed Oct 11 11:53:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddhesh Poyarekar X-Patchwork-Id: 824370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-85635-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="V6VGPHSs"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yBspX2TmBz9sNr for ; Wed, 11 Oct 2017 22:54:28 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=PyaUIC+sUaFf9JlnSVDVCl1ffIFIY1w /XqWAyzx0xfu8aH9bfZUftS6opZPjIlH7x/0k6uOirkhX/IvUu85fS9nTXUf+nq6 bjb1T61Lr9SVbqDC9YH3klAwBaBXeR/UfXm3AuUqYxQVLEKsa6kszpheMrLNcZUh awVR2EekgIys= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; s=default; bh=85GxWeVzN2gDlYeX0oitSEhvMNk=; b=V6VGP HSs6W6aYniMEXVN0aY/ao0RumUSuKpu2B9X2R0iIv/wbOn3LlgGp+jEwjd6QgTM7 3QokU9IQillbTE9Wz5JHOF2hoS0pXJb6TM5HKYYXJE0ezzS4hUklXsScDRt0LYh7 rSqvcnvOcH2xhCCwsEBqFHMKwa9nZWN/am7ptE= Received: (qmail 57555 invoked by alias); 11 Oct 2017 11:54:01 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 57423 invoked by uid 89); 11 Oct 2017 11:54:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_NEUTRAL autolearn=ham version=3.3.2 spammy=Hx-languages-length:2145 X-HELO: homiemail-a120.g.dreamhost.com From: Siddhesh Poyarekar To: libc-alpha@sourceware.org Subject: [PATCH 2/2] aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat Date: Wed, 11 Oct 2017 17:23:44 +0530 Message-Id: <1507722824-9648-2-git-send-email-siddhesh@sourceware.org> In-Reply-To: <1507722824-9648-1-git-send-email-siddhesh@sourceware.org> References: <1507722824-9648-1-git-send-email-siddhesh@sourceware.org> The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the ctr_el0 register, which tells us the minimum observable cache line size by userspace. This typically is the same as the L1 cache line size, but that may not always be true. It could be a higher level cache line size as long as cache cleaning and invalidation work correctly with that line size in userspace. The falkor core for example reports the L2 line size as the dcache line size in CTR_EL0 while also reporting the correct L1 dcache line size via CCSIDR_EL1. * manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat. --- manual/conf.texi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/manual/conf.texi b/manual/conf.texi index 503b240..66a7f35 100644 --- a/manual/conf.texi +++ b/manual/conf.texi @@ -690,6 +690,12 @@ Inquire about associativity of the Level 1 instruction cache. @standards{GNU, unistd.h} Inquire about the line length of the Level 1 instruction cache. +On aarch64, the cache line size returned is the minimum instruction cache line +size observeable by userspace. This is typically the same as the L1 icache +size but on some cores it may not be so. It is specified in the architecture +however that operations such as cache line invalidation are consistent with the +size reported with this variable. + @item _SC_LEVEL1_DCACHE_SIZE @standards{GNU, unistd.h} Inquire about the size of the Level 1 data cache. @@ -702,6 +708,12 @@ Inquire about associativity of the Level 1 data cache. @standards{GNU, unistd.h} Inquire about the line length of the Level 1 data cache. +On aarch64, the cache line size returned is the minimum data cache line size +observeable by userspace. This is typically the same as the L1 dcache size but +on some cores it may not be so. It is specified in the architecture however +that operations such as cache line invalidation are consistent with the size +reported with this variable. + @item _SC_LEVEL2_CACHE_SIZE @standards{GNU, unistd.h} Inquire about the size of the Level 2 cache.