From patchwork Mon Dec 25 10:35:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junxian Zhu X-Patchwork-Id: 1880106 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=PfchJV1N; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SzDqs3Pdqz1ydZ for ; Mon, 25 Dec 2023 21:37:28 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C68F23858422 for ; Mon, 25 Dec 2023 10:37:26 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from va-2-37.ptr.blmpb.com (va-2-37.ptr.blmpb.com [209.127.231.37]) by sourceware.org (Postfix) with ESMTPS id DEADE3858C2F for ; Mon, 25 Dec 2023 10:37:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DEADE3858C2F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DEADE3858C2F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=209.127.231.37 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703500626; cv=none; b=h+AbBU13TrrxHkQxvwsAQrQvsl/qbTS/vj/vDGJv5ac0P2g9mbZGforWo7XlJRxqZwekIPIG6cAo1iM5tWQ5ac5D1CoAd3iQKQkFotjmmT/W5y+vH9e1vAEgU8UZbzYKJUrp2CBdmZkJrCoBO91suXEY+qDEeKOfxwL3yZSCtCk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703500626; c=relaxed/simple; bh=K9NYplk2BDo+0Y4GpTT+OukS8fylKR6JjP9itVQFaoM=; h=DKIM-Signature:From:Date:To:Subject:Message-Id:Mime-Version; b=E1npUcYgB3Ei7E0sKy/ponF6dWEsPNMLpMJGi7fZVolY4f1fTncbcce7gm/MY6dsFr85EeGcRS8yD1elZflOWemDdW9L2Fi8h61TL2zBd7OTl++vofek+Rt/r0DGDT20/Uxq/+CmWemmtUeQD5qff8xelrnHPS2988K5qdCsQO0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1703500619; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=ceqYcnERQtBsGreNlw/WTnFmp4gz9V1HMFHmrK9eY8M=; b=PfchJV1NKtJ+1M9bQCKPdRfL9GVq9LTUV6PMe/WOsbHya16CUaXW/XVxLof/7trd4WufCB 3or92q5b8/01HoVUl/aaGMVjeQtPFyCrBDGtpaoac30zK0/bSgEbNXT+i1t0kLNJPY51+a NkCzoYwvRyVdC7CECMdW9+xQHi8FdcHCxeSFiXReILeQBB8sQ5m2sZJNaV9RmqKsgQ6zWI kP1kctmRipUAG7L5jxWXarnt/Pt9iB9irVribvSUgRNff40VFHxSBOTlc3yPKc2rd1OVYb p9ggf77WUECRpkkp++sm0dS/ivUGSZ0iXooJ6hfn4BTeEQ4gLy7W5w4q1Xkk0g== From: "Junxian Zhu" Date: Mon, 25 Dec 2023 18:35:47 +0800 X-Lms-Return-Path: To: X-Original-From: zhujunxian@oss.cipunited.com Subject: [PATCH 0/2] Add hard-float rounding instructions support for MIPS architecture X-Mailer: git-send-email 2.43.0.windows.1 Received: from localhost.localdomain ([1.192.71.159]) by smtp.feishu.cn with ESMTPS; Mon, 25 Dec 2023 18:36:58 +0800 Cc: , "Junxian Zhu" Message-Id: <20231225103548.1615-2-zhujunxian@oss.cipunited.com> Mime-Version: 1.0 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, DKIM_INVALID, DKIM_SIGNED, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org From: Junxian Zhu Fixing the missing semicolon in define to prevent syntax errors during assembly building. It's to ensure compiled successful after optimizations are applied. Junxian Zhu (2): limb-alias-double.h: Fix missing semicolon MIPS: Hard-float rounding instructions support sysdeps/generic/libm-alias-double.h | 4 +- sysdeps/mips/fpu/Makefile | 12 ++++ sysdeps/mips/fpu/s_ceil.c | 30 ++++++++++ sysdeps/mips/fpu/s_ceil_fpu.S | 90 +++++++++++++++++++++++++++++ sysdeps/mips/fpu/s_ceilf.c | 30 ++++++++++ sysdeps/mips/fpu/s_ceilf_fpu.S | 82 ++++++++++++++++++++++++++ sysdeps/mips/fpu/s_floor.c | 24 ++++++++ sysdeps/mips/fpu/s_floor_fpu.S | 88 ++++++++++++++++++++++++++++ sysdeps/mips/fpu/s_floorf.c | 24 ++++++++ sysdeps/mips/fpu/s_floorf_fpu.S | 80 +++++++++++++++++++++++++ sysdeps/mips/fpu/s_roundeven.c | 24 ++++++++ sysdeps/mips/fpu/s_roundeven_fpu.S | 87 ++++++++++++++++++++++++++++ sysdeps/mips/fpu/s_roundevenf.c | 24 ++++++++ sysdeps/mips/fpu/s_roundevenf_fpu.S | 79 +++++++++++++++++++++++++ sysdeps/mips/fpu/s_trunc.c | 24 ++++++++ sysdeps/mips/fpu/s_trunc_fpu.S | 84 +++++++++++++++++++++++++++ sysdeps/mips/fpu/s_truncf.c | 24 ++++++++ sysdeps/mips/fpu/s_truncf_fpu.S | 76 ++++++++++++++++++++++++ sysdeps/mips/mips32/Implies | 1 + sysdeps/mips/mips64/Implies | 1 + 20 files changed, 886 insertions(+), 2 deletions(-) create mode 100644 sysdeps/mips/fpu/Makefile create mode 100644 sysdeps/mips/fpu/s_ceil.c create mode 100644 sysdeps/mips/fpu/s_ceil_fpu.S create mode 100644 sysdeps/mips/fpu/s_ceilf.c create mode 100644 sysdeps/mips/fpu/s_ceilf_fpu.S create mode 100644 sysdeps/mips/fpu/s_floor.c create mode 100644 sysdeps/mips/fpu/s_floor_fpu.S create mode 100644 sysdeps/mips/fpu/s_floorf.c create mode 100644 sysdeps/mips/fpu/s_floorf_fpu.S create mode 100644 sysdeps/mips/fpu/s_roundeven.c create mode 100644 sysdeps/mips/fpu/s_roundeven_fpu.S create mode 100644 sysdeps/mips/fpu/s_roundevenf.c create mode 100644 sysdeps/mips/fpu/s_roundevenf_fpu.S create mode 100644 sysdeps/mips/fpu/s_trunc.c create mode 100644 sysdeps/mips/fpu/s_trunc_fpu.S create mode 100644 sysdeps/mips/fpu/s_truncf.c create mode 100644 sysdeps/mips/fpu/s_truncf_fpu.S