Message ID | 20231127145603.2339644-1-christoph.muellner@vrull.eu |
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Headers | show
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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id a20-20020a1709063e9400b00a0369e232bfsm5753427ejj.75.2023.11.27.06.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 06:56:08 -0800 (PST) From: Christoph Muellner <christoph.muellner@vrull.eu> To: libc-alpha@sourceware.org, Palmer Dabbelt <palmer@dabbelt.com>, Darius Rad <darius@bluespec.com>, Andrew Waterman <andrew@sifive.com>, Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: =?utf-8?q?Christoph_M=C3=BCllner?= <christoph.muellner@vrull.eu> Subject: [RFC PATCH 0/2] RISC-V: Add dynamic TSO support Date: Mon, 27 Nov 2023 15:56:01 +0100 Message-ID: <20231127145603.2339644-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list <libc-alpha.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/libc-alpha/> List-Post: <mailto:libc-alpha@sourceware.org> List-Help: <mailto:libc-alpha-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=subscribe> Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org |
Series |
RISC-V: Add dynamic TSO support
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From: Christoph Müllner <christoph.muellner@vrull.eu> The upcoming RISC-V Ssdtso specification introduces a bit in the senvcfg CSR to switch the memory consistency model at run-time from RVWMO to TSO (and back). The active consistency model can therefore be switched on a per-hart base and managed by the kernel on a per-process/thread base. A kernel patchset that exposes a prctl API to let user-space processes switch their memory consistency model has been posted recently: https://lore.kernel.org/all/20231124072142.2786653-1-christoph.muellner@vrull.eu/T/#t A remote branch that includes a couple of fixes for that first patchset can be found here (note, that new fixes will be force-pushed into this branch): https://github.com/cmuellner/linux/tree/ssdtso A Ssdtso patchset for QEMU has been posted: https://lists.nongnu.org/archive/html/qemu-devel/2023-11/msg02962.html Additional patches to implement the prctl API for user-mode emulation have been developed as well and can be found here (same note as before): https://github.com/cmuellner/qemu/tree/ssdtso This patchset builds upon this prctl API and extends elf_machine_matches_host() such, that it attempts to switch to TSO mode if the ELF header has EF_RISCV_TSO set, but the machine reports RVWMO as current consistency model. Of course, this is an optional feature, which will fall-back to the current behaviour (rejecting the ELF) if there is any error. The implementation is somewhat inspired by a similar mechanism in the MIPS code (sysdeps/mips/dl-machine-reject-phdr.h) that switches the FP mode if necessary. Following the same pattern, there is also branch for this patchset: https://github.com/cmuellner/glibc/tree/ssdtso Christoph Müllner (2): RISC-V: Move TSO check to elf_machine_matches_host() RISC-V: Attempt to enable TSO mode for TSO binaries sysdeps/riscv/dl-machine.h | 15 +++++++++++++++ sysdeps/unix/sysv/linux/riscv/readelflib.c | 5 ++--- 2 files changed, 17 insertions(+), 3 deletions(-)