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[v3,0/8] x86: Fix AVX2 string functions requiring BMI1, BMI2 or LZCNT (BZ #29611)

Message ID 20221003195944.3274548-1-aurelien@aurel32.net
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Series x86: Fix AVX2 string functions requiring BMI1, BMI2 or LZCNT (BZ #29611) | expand

Message

Aurelien Jarno Oct. 3, 2022, 7:59 p.m. UTC
Some early Intel Haswell CPU have AVX2 instructions, but do not have
BMI1 and BMI2 instructions. Some AVX2 string functions only check for
AVX2, but use BMI1, BMI2 or LZCNT instructions. This patchset tries to
fix that.

While most fixes only change ifunc-impl-list.c, and thus only concerns
the testsuite, the changes to str*cmp and wcs(n)cmp are a real issue
affecting early Intel Haswell CPU, reported to affect Debian Sid and
Fedora Rawhide.

On the other hand, the check for LZCNT in memrchr is purely for
correctness, I am not aware of a CPU implementing AVX2 without LZCNT.

This has been tested by remplacing all BMI1 and BMI2 instructions in the
source code by the "ud2" instruction and disabling the BMI1, BMI2
feature detection, and running the testsuite.

Resolves: BZ #29611

Changes v2 -> v3:
- Change the way patches are split. No code change.

Change v1 -> v2:
- Better scan for BMI2 instructions (shlx and shrx) and BMI1
  instructions (blsmsk) instructions following the feedback from Noah
  Goldstein

Aurelien Jarno (8):
  x86: include BMI1 and BMI2 in x86-64-v3 level
  x86-64: Require BMI2 for AVX2 str(n)casecmp implementations
  x86-64: Require BMI2 for AVX2 strcmp implementation
  x86-64: Require BMI2 for AVX2 strncmp implementation
  x86-64: Require BMI2 for AVX2 wcs(n)cmp implementations
  x86-64: Require BMI2 for AVX2 (raw|w)memchr implementations
  x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation
  x86-64: Require BMI1/BMI2 for AVX2 strrchr and wcsrchr implementations

 sysdeps/x86/get-isa-level.h                 |  2 +
 sysdeps/x86/isa-level.h                     |  2 +
 sysdeps/x86_64/multiarch/ifunc-avx2.h       |  2 +
 sysdeps/x86_64/multiarch/ifunc-impl-list.c  | 86 ++++++++++++++++-----
 sysdeps/x86_64/multiarch/ifunc-strcasecmp.h |  1 +
 sysdeps/x86_64/multiarch/strcmp.c           |  4 +-
 sysdeps/x86_64/multiarch/strncmp.c          |  4 +-
 7 files changed, 76 insertions(+), 25 deletions(-)

Comments

Sunil Pandey Oct. 3, 2022, 8:47 p.m. UTC | #1
v3 looks good to me.

On Mon, Oct 3, 2022 at 12:59 PM Aurelien Jarno <aurelien@aurel32.net> wrote:
>
> Some early Intel Haswell CPU have AVX2 instructions, but do not have
> BMI1 and BMI2 instructions. Some AVX2 string functions only check for
> AVX2, but use BMI1, BMI2 or LZCNT instructions. This patchset tries to
> fix that.
>
> While most fixes only change ifunc-impl-list.c, and thus only concerns
> the testsuite, the changes to str*cmp and wcs(n)cmp are a real issue
> affecting early Intel Haswell CPU, reported to affect Debian Sid and
> Fedora Rawhide.
>
> On the other hand, the check for LZCNT in memrchr is purely for
> correctness, I am not aware of a CPU implementing AVX2 without LZCNT.
>
> This has been tested by remplacing all BMI1 and BMI2 instructions in the
> source code by the "ud2" instruction and disabling the BMI1, BMI2
> feature detection, and running the testsuite.
>
> Resolves: BZ #29611
>
> Changes v2 -> v3:
> - Change the way patches are split. No code change.
>
> Change v1 -> v2:
> - Better scan for BMI2 instructions (shlx and shrx) and BMI1
>   instructions (blsmsk) instructions following the feedback from Noah
>   Goldstein
>
> Aurelien Jarno (8):
>   x86: include BMI1 and BMI2 in x86-64-v3 level
>   x86-64: Require BMI2 for AVX2 str(n)casecmp implementations
>   x86-64: Require BMI2 for AVX2 strcmp implementation
>   x86-64: Require BMI2 for AVX2 strncmp implementation
>   x86-64: Require BMI2 for AVX2 wcs(n)cmp implementations
>   x86-64: Require BMI2 for AVX2 (raw|w)memchr implementations
>   x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation
>   x86-64: Require BMI1/BMI2 for AVX2 strrchr and wcsrchr implementations
>
>  sysdeps/x86/get-isa-level.h                 |  2 +
>  sysdeps/x86/isa-level.h                     |  2 +
>  sysdeps/x86_64/multiarch/ifunc-avx2.h       |  2 +
>  sysdeps/x86_64/multiarch/ifunc-impl-list.c  | 86 ++++++++++++++++-----
>  sysdeps/x86_64/multiarch/ifunc-strcasecmp.h |  1 +
>  sysdeps/x86_64/multiarch/strcmp.c           |  4 +-
>  sysdeps/x86_64/multiarch/strncmp.c          |  4 +-
>  7 files changed, 76 insertions(+), 25 deletions(-)
>
> --
> 2.35.1
>
Noah Goldstein Oct. 3, 2022, 9:11 p.m. UTC | #2
On Mon, Oct 3, 2022 at 12:59 PM Aurelien Jarno <aurelien@aurel32.net> wrote:
>
> Some early Intel Haswell CPU have AVX2 instructions, but do not have
> BMI1 and BMI2 instructions. Some AVX2 string functions only check for
> AVX2, but use BMI1, BMI2 or LZCNT instructions. This patchset tries to
> fix that.
>
> While most fixes only change ifunc-impl-list.c, and thus only concerns
> the testsuite, the changes to str*cmp and wcs(n)cmp are a real issue
> affecting early Intel Haswell CPU, reported to affect Debian Sid and
> Fedora Rawhide.
>
> On the other hand, the check for LZCNT in memrchr is purely for
> correctness, I am not aware of a CPU implementing AVX2 without LZCNT.
>
> This has been tested by remplacing all BMI1 and BMI2 instructions in the
> source code by the "ud2" instruction and disabling the BMI1, BMI2
> feature detection, and running the testsuite.
>
> Resolves: BZ #29611
>
> Changes v2 -> v3:
> - Change the way patches are split. No code change.
>
> Change v1 -> v2:
> - Better scan for BMI2 instructions (shlx and shrx) and BMI1
>   instructions (blsmsk) instructions following the feedback from Noah
>   Goldstein
>
> Aurelien Jarno (8):
>   x86: include BMI1 and BMI2 in x86-64-v3 level
>   x86-64: Require BMI2 for AVX2 str(n)casecmp implementations
>   x86-64: Require BMI2 for AVX2 strcmp implementation
>   x86-64: Require BMI2 for AVX2 strncmp implementation
>   x86-64: Require BMI2 for AVX2 wcs(n)cmp implementations
>   x86-64: Require BMI2 for AVX2 (raw|w)memchr implementations
>   x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation
>   x86-64: Require BMI1/BMI2 for AVX2 strrchr and wcsrchr implementations
>
>  sysdeps/x86/get-isa-level.h                 |  2 +
>  sysdeps/x86/isa-level.h                     |  2 +
>  sysdeps/x86_64/multiarch/ifunc-avx2.h       |  2 +
>  sysdeps/x86_64/multiarch/ifunc-impl-list.c  | 86 ++++++++++++++++-----
>  sysdeps/x86_64/multiarch/ifunc-strcasecmp.h |  1 +
>  sysdeps/x86_64/multiarch/strcmp.c           |  4 +-
>  sysdeps/x86_64/multiarch/strncmp.c          |  4 +-
>  7 files changed, 76 insertions(+), 25 deletions(-)
>
> --
> 2.35.1
>
LGTM.
Reviewed-by: Noah Goldstein  <goldstein.w.n@gmail.com>