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From: " =?gb18030?b?1tO+09Xc?= " <juzhe.zhong@rivai.ai>
To: " =?gb18030?q?pan2=2Eli?= " <pan2.li@intel.com>, " =?gb18030?q?gcc-patch?=
	=?gb18030?q?es?= " <gcc-patches@gcc.gnu.org>
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 " =?gb18030?q?rdapp=2Egcc?= " <rdapp.gcc@gmail.com>,
 " =?gb18030?q?Pan_Li?= " <pan2.li@intel.com>
Subject: =?gb18030?q?=BB=D8=B8=B4=A3=BA=5BPATCH_v1=5D_RISC-V=3A_Bugfix_incor?=
	=?gb18030?q?rect_operand_for_vwsll_auto-vect?=
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lgtm. thanks








 ----------Reply to Message----------
 On Sat, Aug 10, 2024 20:36 PM pan2.li<pan2.li@intel.com&gt; wrote:

  From: Pan Li <pan2.li@intel.com&gt;

This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.
Consider below example.

void vwsll_vv_test (short *restrict dst, char *restrict a,
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; int *restrict b, int n)
{
&nbsp; for (int i = 0; i < n; i++)
&nbsp;&nbsp;&nbsp; dst[i] = a[i] << b[i];
}

It will hit the vwsll pattern with following operands.
operand 0 -&gt; (reg:RVVMF2HI 146 [ vect__7.13 ])
operand 1 -&gt; (reg:RVVMF4QI 165 [ vect_cst__33 ])
operand 2 -&gt; (reg:RVVM1SI 171 [ vect_cst__36 ])

According to the ISA, operand 2 should be the same as operand 1.
Aka operand 2 should have RVVMF4QI mode as above.&nbsp; Thus,&nbsp; add
quad truncation for operand 2 before emit vwsll.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

PR target/116280

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Add quad truncation to
align the mode requirement for vwsll.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr116280-1.c: New test.
* gcc.target/riscv/rvv/base/pr116280-2.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com&gt;
---
&nbsp;gcc/config/riscv/autovec-opt.md&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp; 4 ++++
&nbsp;.../gcc.target/riscv/rvv/base/pr116280-1.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 14 ++++++++++++++
&nbsp;.../gcc.target/riscv/rvv/base/pr116280-2.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 10 ++++++++++
&nbsp;3 files changed, 28 insertions(+)
&nbsp;create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
&nbsp;create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index d7a3cfd4602..4b33a145c17 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1546,6 +1546,10 @@ (define_insn_and_split "*vwsll_zext1_trunc_<mode&gt;"
&nbsp;&nbsp; "&amp;&amp; 1"
&nbsp;&nbsp; [(const_int 0)]
&nbsp;&nbsp; {
+&nbsp;&nbsp;&nbsp; rtx truncated = gen_reg_rtx (<V_QUAD_TRUNC&gt;mode);
+&nbsp;&nbsp;&nbsp; emit_insn (gen_trunc<mode&gt;<v_quad_trunc&gt;2 (truncated, operands[2]));
+&nbsp;&nbsp;&nbsp; operands[2] = truncated;
+
&nbsp;&nbsp;&nbsp;&nbsp; insn_code icode = code_for_pred_vwsll (<V_DOUBLE_TRUNC&gt;mode);
&nbsp;&nbsp;&nbsp;&nbsp; riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
&nbsp;&nbsp;&nbsp;&nbsp; DONE;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
new file mode 100644
index 00000000000..8b8547e2c34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
@@ -0,0 +1,14 @@
+/* Test there is no ICE when compile.&nbsp; */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */
+
+short a;
+char b;
+
+void
+test (int e[][1][1], char f[][1][1][1][1]) {
+&nbsp; for (int g; b;)
+&nbsp;&nbsp;&nbsp; for (;;)
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; for (int h; h < 4073709551572ULL; h += 18446744073709551612U)
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; a = f[2][2][1][4073709551612][1] << e[1][1][g];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
new file mode 100644
index 00000000000..02f2de66eff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
@@ -0,0 +1,10 @@
+/* Test there is no ICE when compile.&nbsp; */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */
+
+void
+test (short *restrict dst, char *restrict a, int *restrict b, int n)
+{
+&nbsp; for (int i = 0; i < n; i++)
+&nbsp;&nbsp;&nbsp; dst[i] = a[i] << b[i];
+}