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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT006.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB2021 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tamar Christina via Gcc-patches From: Tamar Christina Reply-To: Tamar Christina Cc: Richard.Earnshaw@arm.com, nd@arm.com, richard.sandiford@arm.com, Marcus.Shawcroft@arm.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi All, There's no encoding for fcmuo with zero. This restricts the combine patterns from accepting zero registers. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? and GCC 12 branch once unfrozen? Thanks, Tamar gcc/ChangeLog: PR target/106524 * config/aarch64/aarch64-sve.md (*fcmuo_nor_combine, *fcmuo_bic_combine): Don't accept comparisons against zero. gcc/testsuite/ChangeLog: PR target/106524 * gcc.target/aarch64/sve/pr106524.c: New test. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index bd60e65b0c3f05f1c931f03807170f3b9d699de5..e08bee197d8570c3e4e50068febc819d6e85cce0 100644 --- diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index bd60e65b0c3f05f1c931f03807170f3b9d699de5..e08bee197d8570c3e4e50068febc819d6e85cce0 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8231,7 +8231,7 @@ (define_insn_and_split "*fcmuo_bic_combine" [(match_operand: 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (match_operand: 4 "register_operand" "Upa")) (match_dup: 1))) @@ -8267,7 +8267,7 @@ (define_insn_and_split "*fcmuo_nor_combine" [(match_operand: 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (not: (match_operand: 4 "register_operand" "Upa"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c new file mode 100644 index 0000000000000000000000000000000000000000..a9f650f971a5cb5ad993f50aadfcac3a8c664a8b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+sve -O2 -fno-move-loop-invariants" } */ + +void +test__zero (int *restrict dest, int *restrict src, float *a, int count) +{ + int i; + + for (i = 0; i < count; ++i) + dest[i] = !__builtin_isunordered (a[i], 0) ? src[i] : 0; +} --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8231,7 +8231,7 @@ (define_insn_and_split "*fcmuo_bic_combine" [(match_operand: 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (match_operand: 4 "register_operand" "Upa")) (match_dup: 1))) @@ -8267,7 +8267,7 @@ (define_insn_and_split "*fcmuo_nor_combine" [(match_operand: 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (not: (match_operand: 4 "register_operand" "Upa"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c new file mode 100644 index 0000000000000000000000000000000000000000..a9f650f971a5cb5ad993f50aadfcac3a8c664a8b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+sve -O2 -fno-move-loop-invariants" } */ + +void +test__zero (int *restrict dest, int *restrict src, float *a, int count) +{ + int i; + + for (i = 0; i < count; ++i) + dest[i] = !__builtin_isunordered (a[i], 0) ? src[i] : 0; +}