| Message ID | patch-16140-tamar@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | AArch64 sve: Fix fcmuo combine patterns [PR106524] | expand |
> -----Original Message----- > From: Tamar Christina <Tamar.Christina@arm.com> > Sent: Friday, August 12, 2022 11:21 AM > To: gcc-patches@gcc.gnu.org > Cc: nd <nd@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>; > Marcus Shawcroft <Marcus.Shawcroft@arm.com>; Kyrylo Tkachov > <Kyrylo.Tkachov@arm.com>; Richard Sandiford > <Richard.Sandiford@arm.com> > Subject: [PATCH]AArch64 sve: Fix fcmuo combine patterns [PR106524] > > Hi All, > > There's no encoding for fcmuo with zero. This restricts the combine patterns > from accepting zero registers. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? and GCC 12 branch once unfrozen? Ok. Thanks, Kyrill > > Thanks, > Tamar > > gcc/ChangeLog: > > PR target/106524 > * config/aarch64/aarch64-sve.md (*fcmuo<mode>_nor_combine, > *fcmuo<mode>_bic_combine): Don't accept comparisons against > zero. > > gcc/testsuite/ChangeLog: > > PR target/106524 > * gcc.target/aarch64/sve/pr106524.c: New test. > > --- inline copy of patch -- > diff --git a/gcc/config/aarch64/aarch64-sve.md > b/gcc/config/aarch64/aarch64-sve.md > index > bd60e65b0c3f05f1c931f03807170f3b9d699de5..e08bee197d8570c3e4e50068 > febc819d6e85cce0 100644 > --- a/gcc/config/aarch64/aarch64-sve.md > +++ b/gcc/config/aarch64/aarch64-sve.md > @@ -8231,7 +8231,7 @@ (define_insn_and_split > "*fcmuo<mode>_bic_combine" > [(match_operand:<VPRED> 1) > (const_int SVE_KNOWN_PTRUE) > (match_operand:SVE_FULL_F 2 "register_operand" "w") > - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" > "wDz")] > + (match_operand:SVE_FULL_F 3 "register_operand" "w")] > UNSPEC_COND_FCMUO)) > (match_operand:<VPRED> 4 "register_operand" "Upa")) > (match_dup:<VPRED> 1))) > @@ -8267,7 +8267,7 @@ (define_insn_and_split > "*fcmuo<mode>_nor_combine" > [(match_operand:<VPRED> 1) > (const_int SVE_KNOWN_PTRUE) > (match_operand:SVE_FULL_F 2 "register_operand" "w") > - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" > "wDz")] > + (match_operand:SVE_FULL_F 3 "register_operand" "w")] > UNSPEC_COND_FCMUO)) > (not:<VPRED> > (match_operand:<VPRED> 4 "register_operand" "Upa"))) > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c > b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..a9f650f971a5cb5ad993f50a > adfcac3a8c664a8b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=armv8-a+sve -O2 -fno-move-loop-invariants" } */ > + > +void > +test__zero (int *restrict dest, int *restrict src, float *a, int count) > +{ > + int i; > + > + for (i = 0; i < count; ++i) > + dest[i] = !__builtin_isunordered (a[i], 0) ? src[i] : 0; > +} > > > > > --
--- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8231,7 +8231,7 @@ (define_insn_and_split "*fcmuo<mode>_bic_combine" [(match_operand:<VPRED> 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (match_operand:<VPRED> 4 "register_operand" "Upa")) (match_dup:<VPRED> 1))) @@ -8267,7 +8267,7 @@ (define_insn_and_split "*fcmuo<mode>_nor_combine" [(match_operand:<VPRED> 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (not:<VPRED> (match_operand:<VPRED> 4 "register_operand" "Upa"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c new file mode 100644 index 0000000000000000000000000000000000000000..a9f650f971a5cb5ad993f50aadfcac3a8c664a8b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+sve -O2 -fno-move-loop-invariants" } */ + +void +test__zero (int *restrict dest, int *restrict src, float *a, int count) +{ + int i; + + for (i = 0; i < count; ++i) + dest[i] = !__builtin_isunordered (a[i], 0) ? src[i] : 0; +}
Hi All, There's no encoding for fcmuo with zero. This restricts the combine patterns from accepting zero registers. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? and GCC 12 branch once unfrozen? Thanks, Tamar gcc/ChangeLog: PR target/106524 * config/aarch64/aarch64-sve.md (*fcmuo<mode>_nor_combine, *fcmuo<mode>_bic_combine): Don't accept comparisons against zero. gcc/testsuite/ChangeLog: PR target/106524 * gcc.target/aarch64/sve/pr106524.c: New test. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index bd60e65b0c3f05f1c931f03807170f3b9d699de5..e08bee197d8570c3e4e50068febc819d6e85cce0 100644 -- diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index bd60e65b0c3f05f1c931f03807170f3b9d699de5..e08bee197d8570c3e4e50068febc819d6e85cce0 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8231,7 +8231,7 @@ (define_insn_and_split "*fcmuo<mode>_bic_combine" [(match_operand:<VPRED> 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (match_operand:<VPRED> 4 "register_operand" "Upa")) (match_dup:<VPRED> 1))) @@ -8267,7 +8267,7 @@ (define_insn_and_split "*fcmuo<mode>_nor_combine" [(match_operand:<VPRED> 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (not:<VPRED> (match_operand:<VPRED> 4 "register_operand" "Upa"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c new file mode 100644 index 0000000000000000000000000000000000000000..a9f650f971a5cb5ad993f50aadfcac3a8c664a8b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+sve -O2 -fno-move-loop-invariants" } */ + +void +test__zero (int *restrict dest, int *restrict src, float *a, int count) +{ + int i; + + for (i = 0; i < count; ++i) + dest[i] = !__builtin_isunordered (a[i], 0) ? src[i] : 0; +}