From patchwork Sat Apr 13 18:21:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Schwab X-Patchwork-Id: 236386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 9DBAC2C009D for ; Sun, 14 Apr 2013 04:21:18 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:cc:date:message-id:mime-version:content-type; q=dns; s=default; b=gkye6ZrFYL8NIXFw6lFSJ5nqUtEfSRJDS4exl6uwmLY6ANRw3y JtukioqbNwGGRydBN/luVVXBe+C3kfVy9Mtl8eRm38mV49TsaUHsym/a+hEO3dwd KYtfj1CCQe509uE/EMP+pXZYJuQ/BDhaQ7+UNYwDjXNQNa0Za9JaGjmM8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:cc:date:message-id:mime-version:content-type; s= default; bh=3eC0yLGKA/Sj6q59ZjQSjZj7SnA=; b=dR476Wi1+Mn9Fihl2lzd TV+1s3+eGY3q+iozYA7RUQR3tghQczfDPIZatnHsaaImiZ684ek5EWGu+V0Kr+2/ gq6LALf6rmc6atj8KgYUFpESyeUcMV25ST0Ixg7d4muTdsPPvJwL0rZ0QzVaLxvc YTgLMTu7EDJWxkASCf/H7Ks= Received: (qmail 18715 invoked by alias); 13 Apr 2013 18:21:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 18700 invoked by uid 89); 13 Apr 2013 18:21:11 -0000 X-Spam-SWARE-Status: No, score=-6.1 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, TW_BF, TW_IB autolearn=ham version=3.3.1 X-Spam-User: qpsmtpd, 2 recipients Received: from cantor2.suse.de (HELO mx2.suse.de) (195.135.220.15) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Sat, 13 Apr 2013 18:21:10 +0000 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 551B9A5237; Sat, 13 Apr 2013 20:21:08 +0200 (CEST) From: Andreas Schwab To: java-patches@gcc.gnu.org Subject: [PATCH] Enable java for aarch64 Cc: gcc-patches@gcc.gnu.org X-Yow: My mind is a potato field... Date: Sat, 13 Apr 2013 20:21:08 +0200 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 This enables building java for aarch64. Most of the configuration bits were copied from arm. === libjava Summary === # of expected passes 2533 # of unexpected failures 29 # of untested testcases 25 Andreas. * configure.ac (aarch64-*-*): Don't disable java. * configure: Regenerate. libjava/: * configure.host: Add support for aarch64. * sysdep/aarch64/locks.h: New file. libjava/classpath/: * native/fdlibm/ieeefp.h: Add support for aarch64. --- configure | 2 ++ configure.ac | 2 ++ libjava/classpath/native/fdlibm/ieeefp.h | 8 +++++ libjava/configure.host | 8 ++++- libjava/sysdep/aarch64/locks.h | 57 ++++++++++++++++++++++++++++++++ 5 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 libjava/sysdep/aarch64/locks.h diff --git a/configure b/configure index d809535..e161cad 100755 --- a/configure +++ b/configure @@ -3272,6 +3272,8 @@ esac # Disable Java if libffi is not supported. case "${target}" in + aarch64-*-*) + ;; alpha*-*-*) ;; arm*-*-*) diff --git a/configure.ac b/configure.ac index 48ec1aa..bec489f 100644 --- a/configure.ac +++ b/configure.ac @@ -611,6 +611,8 @@ esac # Disable Java if libffi is not supported. case "${target}" in + aarch64-*-*) + ;; alpha*-*-*) ;; arm*-*-*) diff --git a/libjava/classpath/native/fdlibm/ieeefp.h b/libjava/classpath/native/fdlibm/ieeefp.h index c230bbb..7ef2ae7e 100644 --- a/libjava/classpath/native/fdlibm/ieeefp.h +++ b/libjava/classpath/native/fdlibm/ieeefp.h @@ -4,6 +4,14 @@ #ifndef __IEEE_BIG_ENDIAN #ifndef __IEEE_LITTLE_ENDIAN +#ifdef __aarch64__ +#ifdef __AARCH64EB__ +#define __IEEE_BIG_ENDIAN +#else +#define __IEEE_LITTLE_ENDIAN +#endif +#endif + #ifdef __alpha__ #define __IEEE_LITTLE_ENDIAN #endif diff --git a/libjava/configure.host b/libjava/configure.host index 0c3b41c..96f86fe 100644 --- a/libjava/configure.host +++ b/libjava/configure.host @@ -81,6 +81,11 @@ ATOMICSPEC= # This case statement supports per-CPU defaults. case "${host}" in + aarch64*-linux*) + libgcj_interpreter=yes + sysdeps_dir=aarch64 + ATOMICSPEC=-fuse-atomic-builtins + ;; arm*-elf) with_libffi_default=no PROCESS=Ecos @@ -224,7 +229,8 @@ case "${host}" in x86_64*-linux* | \ hppa*-linux* | \ m68k*-linux* | \ - sh-linux* | sh[34]*-linux*) + sh-linux* | sh[34]*-linux* | \ + aarch64*-linux*) can_unwind_signal=yes libgcj_ld_symbolic='-Wl,-Bsymbolic' if test x$slow_pthread_self = xyes \ diff --git a/libjava/sysdep/aarch64/locks.h b/libjava/sysdep/aarch64/locks.h new file mode 100644 index 0000000..f91473d --- /dev/null +++ b/libjava/sysdep/aarch64/locks.h @@ -0,0 +1,57 @@ +// locks.h - Thread synchronization primitives. AArch64 implementation. + +#ifndef __SYSDEP_LOCKS_H__ +#define __SYSDEP_LOCKS_H__ + +typedef size_t obj_addr_t; /* Integer type big enough for object */ + /* address. */ + +// Atomically replace *addr by new_val if it was initially equal to old. +// Return true if the comparison succeeded. +// Assumed to have acquire semantics, i.e. later memory operations +// cannot execute before the compare_and_swap finishes. +inline static bool +compare_and_swap(volatile obj_addr_t *addr, + obj_addr_t old, + obj_addr_t new_val) +{ + return __sync_bool_compare_and_swap(addr, old, new_val); +} + +// Set *addr to new_val with release semantics, i.e. making sure +// that prior loads and stores complete before this +// assignment. +inline static void +release_set(volatile obj_addr_t *addr, obj_addr_t new_val) +{ + __sync_synchronize(); + *addr = new_val; +} + +// Compare_and_swap with release semantics instead of acquire semantics. +// On many architecture, the operation makes both guarantees, so the +// implementation can be the same. +inline static bool +compare_and_swap_release(volatile obj_addr_t *addr, + obj_addr_t old, + obj_addr_t new_val) +{ + return __sync_bool_compare_and_swap(addr, old, new_val); +} + +// Ensure that subsequent instructions do not execute on stale +// data that was loaded from memory before the barrier. +inline static void +read_barrier() +{ + __sync_synchronize(); +} + +// Ensure that prior stores to memory are completed with respect to other +// processors. +inline static void +write_barrier() +{ + __sync_synchronize(); +} +#endif