From patchwork Fri Nov 17 17:24:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1865151 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SX3ft5GfBz1yRM for ; Sat, 18 Nov 2023 04:24:22 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DE0BC385828F for ; Fri, 17 Nov 2023 17:24:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id BB1A33858C5F for ; Fri, 17 Nov 2023 17:24:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BB1A33858C5F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BB1A33858C5F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700241849; cv=none; b=kyTNYWnRJbWewKLAe1DqqFd1X7OcSpvHygoHeayTKKk+ryg9G4IEe7Z8t0P8//h1TPPNCzyt/mt4tOKQYVs/ZmWqyndxJwWFyIRMLXbfUu5nWt7wKBq5F2zMdoAbUUL3S9MLzMNpn8oPD+ihbKGBoV84tH7TRtIRot15DSiZYgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700241849; c=relaxed/simple; bh=JxXA6LmHEDfZYSqx952su+CzAXYHr1wdGs4F0DrIET0=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=xUtb4nLDTs93rxiQA0xzZGQ1nYaBaDHQdp388p6ZuHiQP8CV2VAIhE47lv+uBdaINvH39mT9qlQxX2tqNfFMu3Ti9CD8D9ERSOU+DmKsETztZxV4Q7mvzY3AD5DblTPeAsKBmA6qpYH9iq4EomxXVJJ2D6q7xcwF4nrjleRxctw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6D7B01477 for ; Fri, 17 Nov 2023 09:24:53 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 090233F73F for ; Fri, 17 Nov 2023 09:24:06 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH 01/21] aarch64: Generalise require_immediate_lane_index References: Date: Fri, 17 Nov 2023 17:24:05 +0000 In-Reply-To: (Richard Sandiford's message of "Fri, 17 Nov 2023 17:23:28 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-23.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org require_immediate_lane_index previously hard-coded the assumption that the group size is determined by the argument immediately before the index. However, for SME, there are cases where it should be determined by an earlier argument instead. gcc/ * config/aarch64/aarch64-sve-builtins.h: (function_checker::require_immediate_lane_index): Add an argument for the index of the indexed vector argument. * config/aarch64/aarch64-sve-builtins.cc (function_checker::require_immediate_lane_index): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.cc (ternary_bfloat_lane_base::check): Update accordingly. (ternary_qq_lane_base::check): Likewise. (binary_lane_def::check): Likewise. (binary_long_lane_def::check): Likewise. (ternary_lane_def::check): Likewise. (ternary_lane_rotate_def::check): Likewise. (ternary_long_lane_def::check): Likewise. (ternary_qq_lane_rotate_def::check): Likewise. --- .../aarch64/aarch64-sve-builtins-shapes.cc | 16 ++++++++-------- gcc/config/aarch64/aarch64-sve-builtins.cc | 18 ++++++++++++------ gcc/config/aarch64/aarch64-sve-builtins.h | 3 ++- 3 files changed, 22 insertions(+), 15 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc index af816c4c9e7..1646afc7a0d 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc @@ -941,7 +941,7 @@ struct ternary_bfloat_lane_base bool check (function_checker &c) const override { - return c.require_immediate_lane_index (3, N); + return c.require_immediate_lane_index (3, 2, N); } }; @@ -956,7 +956,7 @@ struct ternary_qq_lane_base bool check (function_checker &c) const override { - return c.require_immediate_lane_index (3, 4); + return c.require_immediate_lane_index (3, 0); } }; @@ -1123,7 +1123,7 @@ struct binary_lane_def : public overloaded_base<0> bool check (function_checker &c) const override { - return c.require_immediate_lane_index (2); + return c.require_immediate_lane_index (2, 1); } }; SHAPE (binary_lane) @@ -1162,7 +1162,7 @@ struct binary_long_lane_def : public overloaded_base<0> bool check (function_checker &c) const override { - return c.require_immediate_lane_index (2); + return c.require_immediate_lane_index (2, 1); } }; SHAPE (binary_long_lane) @@ -2817,7 +2817,7 @@ struct ternary_lane_def : public overloaded_base<0> bool check (function_checker &c) const override { - return c.require_immediate_lane_index (3); + return c.require_immediate_lane_index (3, 2); } }; SHAPE (ternary_lane) @@ -2845,7 +2845,7 @@ struct ternary_lane_rotate_def : public overloaded_base<0> bool check (function_checker &c) const override { - return (c.require_immediate_lane_index (3, 2) + return (c.require_immediate_lane_index (3, 2, 2) && c.require_immediate_one_of (4, 0, 90, 180, 270)); } }; @@ -2868,7 +2868,7 @@ struct ternary_long_lane_def bool check (function_checker &c) const override { - return c.require_immediate_lane_index (3); + return c.require_immediate_lane_index (3, 2); } }; SHAPE (ternary_long_lane) @@ -2965,7 +2965,7 @@ struct ternary_qq_lane_rotate_def : public overloaded_base<0> bool check (function_checker &c) const override { - return (c.require_immediate_lane_index (3, 4) + return (c.require_immediate_lane_index (3, 0) && c.require_immediate_one_of (4, 0, 90, 180, 270)); } }; diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc index 161a14edde7..75a51565ed2 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc @@ -2440,20 +2440,26 @@ function_checker::require_immediate_enum (unsigned int rel_argno, tree type) return false; } -/* Check that argument REL_ARGNO is suitable for indexing argument - REL_ARGNO - 1, in groups of GROUP_SIZE elements. REL_ARGNO counts - from the end of the predication arguments. */ +/* The intrinsic conceptually divides vector argument REL_VEC_ARGNO into + groups of GROUP_SIZE elements. Return true if argument REL_ARGNO is + a suitable constant index for selecting one of these groups. The + selection happens within a 128-bit quadword, rather than the whole vector. + + REL_ARGNO and REL_VEC_ARGNO count from the end of the predication + arguments. */ bool function_checker::require_immediate_lane_index (unsigned int rel_argno, + unsigned int rel_vec_argno, unsigned int group_size) { unsigned int argno = m_base_arg + rel_argno; if (!argument_exists_p (argno)) return true; - /* Get the type of the previous argument. tree_argument_type wants a - 1-based number, whereas ARGNO is 0-based. */ - machine_mode mode = TYPE_MODE (type_argument_type (m_fntype, argno)); + /* Get the type of the vector argument. tree_argument_type wants a + 1-based number, whereas VEC_ARGNO is 0-based. */ + unsigned int vec_argno = m_base_arg + rel_vec_argno; + machine_mode mode = TYPE_MODE (type_argument_type (m_fntype, vec_argno + 1)); gcc_assert (VECTOR_MODE_P (mode)); unsigned int nlanes = 128 / (group_size * GET_MODE_UNIT_BITSIZE (mode)); return require_immediate_range (rel_argno, 0, nlanes - 1); diff --git a/gcc/config/aarch64/aarch64-sve-builtins.h b/gcc/config/aarch64/aarch64-sve-builtins.h index a301570b82e..99bfd906a07 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.h +++ b/gcc/config/aarch64/aarch64-sve-builtins.h @@ -463,7 +463,8 @@ public: bool require_immediate_either_or (unsigned int, HOST_WIDE_INT, HOST_WIDE_INT); bool require_immediate_enum (unsigned int, tree); - bool require_immediate_lane_index (unsigned int, unsigned int = 1); + bool require_immediate_lane_index (unsigned int, unsigned int, + unsigned int = 1); bool require_immediate_one_of (unsigned int, HOST_WIDE_INT, HOST_WIDE_INT, HOST_WIDE_INT, HOST_WIDE_INT); bool require_immediate_range (unsigned int, HOST_WIDE_INT, HOST_WIDE_INT);