diff mbox series

[committed] testsuite: Fix Advanced SIMD failures for SVE

Message ID mptwntcc1t1.fsf@arm.com
State New
Headers show
Series [committed] testsuite: Fix Advanced SIMD failures for SVE | expand

Commit Message

Richard Sandiford April 8, 2021, 2:02 p.m. UTC 
This patch just adds some missing +nosve directives to Advanced
SIMD vectorisation tests.

Tested on aarch64-linux-gnu, pushed to trunk.

Richard


gcc/testsuite/
	* gcc.target/aarch64/asimd-mull-elem.c: Add +nosve.
	* gcc.target/aarch64/pr98772.c: Likewise.
	* gcc.target/aarch64/simd/vect_su_add_sub.c: Likewise.
---
 gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c      | 2 ++
 gcc/testsuite/gcc.target/aarch64/pr98772.c              | 3 +++
 gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c | 2 ++
 3 files changed, 7 insertions(+)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c b/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c
index 513721cee0c..8ee7d118251 100644
--- a/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c
+++ b/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c
@@ -3,6 +3,8 @@ 
 /* { dg-require-effective-target vect_float } */
 /* { dg-options "-Ofast" } */
 
+#pragma GCC target "+nosve"
+
 #include <arm_neon.h>
 
 void s_mult_i (int32_t* restrict res, int32_t* restrict a, int32_t b)
diff --git a/gcc/testsuite/gcc.target/aarch64/pr98772.c b/gcc/testsuite/gcc.target/aarch64/pr98772.c
index 663221514e9..8259251a7c0 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr98772.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr98772.c
@@ -1,5 +1,8 @@ 
 /* { dg-do run } */
 /* { dg-options "-O3 -save-temps" } */
+
+#pragma GCC target "+nosve"
+
 #include <stdint.h>
 #include <string.h>
 
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c
index 921c5f15c74..4abb8e92cb4 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c
@@ -1,6 +1,8 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O3" } */
 
+#pragma GCC target "+nosve"
+
 typedef int __attribute__ ((mode (SI))) int32_t;
 typedef int __attribute__ ((mode (DI))) int64_t;
 typedef unsigned __attribute__ ((mode (SI))) size_t;