From patchwork Tue Jul 20 14:44:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1507592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=yeEXqTPH; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GThMW0cWDz9sWd for ; Wed, 21 Jul 2021 00:45:11 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C40C3398306A for ; Tue, 20 Jul 2021 14:45:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C40C3398306A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1626792308; bh=f/A+34aWVXZszAeVKhNBYkSkwuYsVb8h5kY6wtRZf7A=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=yeEXqTPHj29GPJIxvGCmbYOuCNhUnUeoqTYZjJAxlDoQOgDr5mq/3c26YlMFOIDg7 i4Ed0BonUOmWaZYrEo/qwqFvlakenXcV+G9rKNxKQyWXAnTEO53LcEvlSmbMQC82Ew pYOdhuzDhnzBlYLPINKoTsu4leGbQK8w54P++zaA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 41569398306C for ; Tue, 20 Jul 2021 14:44:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 41569398306C Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB8201FB for ; Tue, 20 Jul 2021 07:44:21 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 722BF3F694 for ; Tue, 20 Jul 2021 07:44:21 -0700 (PDT) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed] aarch64: Tweak old vect-* tests to avoid new FAILs Date: Tue, 20 Jul 2021 15:44:20 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" I'm not sure what these test were originally designed to test. vaddv and vmaxv seem to be testing for vectorisation, with associated scan-assembler tests. But they use arm_neon.h functions to test the results, which would presumably also trip many of the scans. That was probably what the split into vect-fmax-fmin.c and vect-fmaxv-fminv-compile.c was supposed to avoid. Anyway, the tests started failing after the recent change to allow staged reductions for epilogue loops. And epilogues came into play because the reduction loops iterate LANES-1 rather than LANES times. (vmaxv was trying to iterate LANES times, but the gimple optimisers outsmarted it. The other two explicitly had a count of LANES-1.) Just suppressing epilogues causes other issues for vaddv and vmaxv. The easiest fix therefore seemed to be to use an asm to hide the initial value of the vmaxv loop (so that it really does iterate LANES times) and then make the others match that style. Tested on aarch64-linux-gnu & pushed. Richard gcc/testsuite/ PR testsuite/101506 * gcc.target/aarch64/vect-vmaxv.c: Use an asm to hide the true initial value of the reduction from the vectorizer. * gcc.target/aarch64/vect-vaddv.c: Likewise. Make the vector loop operate on exactly LANES (rather than LANES-1) iterations. * gcc.target/aarch64/vect-fmaxv-fminv.x: Likewise. --- .../gcc.target/aarch64/vect-fmaxv-fminv.x | 20 +++++++++++-------- gcc/testsuite/gcc.target/aarch64/vect-vaddv.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c | 2 +- 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x b/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x index 0bc6ba494cf..d3ba31c425a 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x +++ b/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x @@ -5,8 +5,9 @@ typedef double *__restrict__ pRF64; float maxv_f32 (pRF32 a) { int i; - float s = a[0]; - for (i=1;i<8;i++) + float s; + asm ("" : "=w" (s) : "0" (a[0])); + for (i=0;i<8;i++) s = (s > a[i] ? s : a[i]); return s; @@ -15,8 +16,9 @@ float maxv_f32 (pRF32 a) float minv_f32 (pRF32 a) { int i; - float s = a[0]; - for (i=1;i<16;i++) + float s; + asm ("" : "=w" (s) : "0" (a[0])); + for (i=0;i<16;i++) s = (s < a[i] ? s : a[i]); return s; @@ -25,8 +27,9 @@ float minv_f32 (pRF32 a) double maxv_f64 (pRF64 a) { int i; - double s = a[0]; - for (i=1;i<8;i++) + double s; + asm ("" : "=w" (s) : "0" (a[0])); + for (i=0;i<8;i++) s = (s > a[i] ? s : a[i]); return s; @@ -35,8 +38,9 @@ double maxv_f64 (pRF64 a) double minv_f64 (pRF64 a) { int i; - double s = a[0]; - for (i=1;i<16;i++) + double s; + asm ("" : "=w" (s) : "0" (a[0])); + for (i=0;i<16;i++) s = (s < a[i] ? s : a[i]); return s; diff --git a/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c b/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c index 41e9157dbec..3a12ae9706a 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c @@ -57,8 +57,8 @@ test_vaddv##SUFFIX##_##TYPE##x##LANES##_t (void) \ /* Calculate linearly. */ \ for (i = 0; i < moves; i++) \ { \ - out_l[i] = input_##TYPE[i]; \ - for (j = 1; j < LANES; j++) \ + asm ("" : "=r" (out_l[i]) : "0" (0)); \ + for (j = 0; j < LANES; j++) \ out_l[i] += input_##TYPE[i + j]; \ } \ \ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c b/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c index 4280834ec4a..1bdea890d3e 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c @@ -36,7 +36,7 @@ test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void) \ /* Calculate linearly. */ \ for (i = 0; i < moves; i++) \ { \ - out_l[i] = input_##TYPE[i]; \ + asm ("" : "=r" (out_l[i]) : "0" (input_##TYPE[i])); \ for (j = 0; j < LANES; j++) \ out_l[i] = input_##TYPE[i + j] CMP_OP out_l[i] ? \ input_##TYPE[i + j] : out_l[i]; \