From patchwork Tue Jan 30 09:34:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1892723 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TPKlD67zXz23dQ for ; Tue, 30 Jan 2024 20:35:04 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C9BBE3857B94 for ; Tue, 30 Jan 2024 09:35:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id EEEAB385802B for ; Tue, 30 Jan 2024 09:34:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EEEAB385802B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EEEAB385802B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706607275; cv=none; b=oZsdTVPCZ1cWx3dN/ixmDeWNkeGQiUljpDsaIfoMDE1e3LEpTifsrY5/l+RTx4KwVig1JCoOtFeVxXJSg0ishN1/gn0bL51Lx/3BvjmShH4Sib6spg5avHbCpxjU80nvP5RKj20GQ1fGl/CqxCzPH5IYHq5DbnrwXYjvc8gXQIg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706607275; c=relaxed/simple; bh=E+6KfYJG27QNtp4jIbkQlM0+QC8mcyul8+THLEpJSNg=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=exxIOwMNGTh3dB1DvaThcstIg9JnXNwTv8MvklqZkdLM+2xfZWhwc/HYAOFIaT1Rfa+vVEXguHq8dadFrFH74qwb7x6NP0NyO9sXRfy9RjcMxjr5fGoAn+gAP1ZBXQg2tLs5YszHuYpk1w+2f0STHoj5fL24Yfi7jofou6IGr4A= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5CB54DA7 for ; Tue, 30 Jan 2024 01:35:16 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 50D603F738 for ; Tue, 30 Jan 2024 01:34:32 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [pushed] aarch64: Avoid allocating FPRs to address registers [PR113623] Date: Tue, 30 Jan 2024 09:34:31 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-21.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org For something like: void foo (void) { int *ptr; asm volatile ("%0" : "=w" (ptr)); asm volatile ("%0" :: "m" (*ptr)); } early-ra would allocate ptr to an FPR for the first asm, thus leaving an FPR address in the second asm. The address was then reloaded by LRA to make it valid. But early-ra shouldn't be allocating at all in that kind of situation. Doing so caused the ICE in the PR (with LDP fusion). Fixed by making sure that we record address references as GPR references. Tested on aarch64-linux-gnu & pushed. Richard gcc/ PR target/113623 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns): Mark all registers that occur in addresses as needing a GPR. gcc/testsuite/ PR target/113623 * gcc.c-torture/compile/pr113623.c: New test. --- gcc/config/aarch64/aarch64-early-ra.cc | 9 ++ .../gcc.c-torture/compile/pr113623.c | 137 ++++++++++++++++++ 2 files changed, 146 insertions(+) create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr113623.c diff --git a/gcc/config/aarch64/aarch64-early-ra.cc b/gcc/config/aarch64/aarch64-early-ra.cc index 028296639b8..1a03d86e94b 100644 --- a/gcc/config/aarch64/aarch64-early-ra.cc +++ b/gcc/config/aarch64/aarch64-early-ra.cc @@ -1173,6 +1173,15 @@ early_ra::preprocess_insns () if (!NONDEBUG_INSN_P (insn)) continue; + // Mark all registers that occur in addresses as needing a GPR. + vec_rtx_properties properties; + properties.add_insn (insn, true); + for (rtx_obj_reference ref : properties.refs ()) + if (ref.is_reg () + && ref.in_address () + && !HARD_REGISTER_NUM_P (ref.regno)) + m_pseudo_regs[ref.regno].flags |= ALLOWS_NONFPR | NEEDS_NONFPR; + if (GET_CODE (PATTERN (insn)) == USE || GET_CODE (PATTERN (insn)) == CLOBBER) continue; diff --git a/gcc/testsuite/gcc.c-torture/compile/pr113623.c b/gcc/testsuite/gcc.c-torture/compile/pr113623.c new file mode 100644 index 00000000000..ed33890054e --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr113623.c @@ -0,0 +1,137 @@ +typedef struct A A; +typedef struct B B; +struct A { char *a; long b; }; +enum { C, D }; +typedef struct { A *c; A *d; } E; +typedef enum { F } G; +typedef enum { H } I; +struct B { A *e, *f, *g, *h; char i; } j; +int k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z, aa, ab, ac, ad, ae, af; +int ag, ah, ai, aj, ak, al, am, an, ao, ap; +E aq; +G ar; +I as; +char at; + +static int +foo (char *c, long d) +{ + switch (d) { + case 7: + switch (c[6]) + case 'd': + if (ao) + case 'h': + if (an) + case 'r': + if (am) + case 's': + if (al) + if (ak) + return C; + /* FALLTHRU */ + case 8: + switch (c[7]) + case 'e': + if (aj) + case 'h': + if (ai) + case 'n': + if (ah) + case 'y': + if (ag) + case 9: + switch (c[8]) + case 'l': + case 0: + switch (c[9]) + case 'e': + if (af) + if (ae) + case 'n': + if (ad) + case 't': + if (ac) + case 'y': + if (ab) + case 1: + switch (c[0]) + case 'r': + case 2: + switch (c[1]) + case 'e': + case 3: + switch (c[2]) + case 'd': + if (aa) + case 'e': + if (z) + case 'h': + if (y) + case 'l': + if (x) + case 'n': + if (w) + case 's': + if (v) + case 4: + switch (c[3]) + case 'h': + if (u) + case 't': + if (t) + case 5: + switch (c[4]) + case 'e': + if (s) + case 'g': + if (r) + case 6: + switch (c[5]) + case 'e': + if (q) + if (p) + case 'g': + if (o) + case 'n': + if (n) + if (m) + case 7: + switch (c[6]) + case 'e': + if (l) + case 'g': + if (k) + return D; + } + return 0; +} + +void bar (void); + +static int +baz (B *x) +{ + aq.c = x->e; + aq.d = x->f; + ap = foo (x->e->a, x->e->b); + if (x->i) + bar (); + x->g = aq.c; + x->h = aq.d; + return 0; +} + +void +qux (void) +{ + for (; at;) + switch (as) + { + case H: + baz (&j); + j.f->b = 0; + if (ar) + baz (&j); + } +}