From patchwork Mon Jul 22 15:43:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1963301 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WSPhd1L1Tz1yYm for ; Tue, 23 Jul 2024 01:44:01 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 62E3C385DDD6 for ; Mon, 22 Jul 2024 15:43:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id EE0213851C30 for ; Mon, 22 Jul 2024 15:43:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EE0213851C30 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EE0213851C30 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721663021; cv=none; b=MS8tOlN335pe9d2JI2pUdLgSirY2tegO/VLb0JrBXVBs/1uBET8XtyLXu7/FZXDuKOBz6YzWKI3dfRCbB4Sa4aLSPMv6L4Emz6n41is/a7yvvSCqeQWUKdJtM/4AukE6gHvJogfoZdRliSc2DCjqn/GRmj2yOwKU0ynt/MqhhHQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721663021; c=relaxed/simple; bh=Y3vaVXc3q16rKYl5qPG5jJNNdC2v7xtP4VGjveNOKX8=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=oCV9IUg60X+gZpYisgAKMNvzzapvW6z6arcmaa/gsZg9baGXRXIDCm6TLCbsMzz3CW8Q8sRlnhq2qnYeYHgzfAvvAizE2oLODLkvdFxSNzIsJN16x168Z/OwNuzy5CehKhC+TzSaVhOfjYEhM74LG+/uTCFW0sOouD31jLbHjjI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2DD0FFEC for ; Mon, 22 Jul 2024 08:44:05 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 65D963F5A1 for ; Mon, 22 Jul 2024 08:43:39 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [pushed] aarch64: Tighten aarch64_simd_mem_operand_p [PR115969] Date: Mon, 22 Jul 2024 16:43:38 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) MIME-Version: 1.0 X-Spam-Status: No, score=-19.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org aarch64_simd_mem_operand_p checked for a memory with a POST_INC or REG address, but it didn't check what kind of register was being used. This meant that it allowed DImode FPRs as well as GPRs. I wondered about rewriting it to use aarch64_classify_address, but this one-line fix seemed simpler. The structure then mirrors the existing early exit in aarch64_classify_address itself: /* On LE, for AdvSIMD, don't support anything other than POST_INC or REG addressing. */ if (advsimd_struct_p && TARGET_SIMD && !BYTES_BIG_ENDIAN && (code != POST_INC && code != REG)) return false; Tested on aarch64-linux-gnu & pushed. Richard gcc/ PR target/115969 * config/aarch64/aarch64.cc (aarch64_simd_mem_operand_p): Require the operand to be a legitimate memory_operand. gcc/testsuite/ PR target/115969 * gcc.target/aarch64/pr115969.c: New test. --- gcc/config/aarch64/aarch64.cc | 5 +++-- gcc/testsuite/gcc.target/aarch64/pr115969.c | 8 ++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr115969.c diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 89eb66348f7..9e51236ce9f 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -23377,8 +23377,9 @@ aarch64_endian_lane_rtx (machine_mode mode, unsigned int n) bool aarch64_simd_mem_operand_p (rtx op) { - return MEM_P (op) && (GET_CODE (XEXP (op, 0)) == POST_INC - || REG_P (XEXP (op, 0))); + return (MEM_P (op) + && (GET_CODE (XEXP (op, 0)) == POST_INC || REG_P (XEXP (op, 0))) + && memory_operand (op, VOIDmode)); } /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr115969.c b/gcc/testsuite/gcc.target/aarch64/pr115969.c new file mode 100644 index 00000000000..ea46626e617 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr115969.c @@ -0,0 +1,8 @@ +/* { dg-options "-O2" } */ + +#define vec8 __attribute__((vector_size(8))) +vec8 int f(int *a) +{ + asm("":"+w"(a)); + return (vec8 int){a[0], a[0]}; +}