From patchwork Fri Sep 15 08:21:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1834744 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=cpo7s2KO; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rn6c61ZcFz1ypK for ; Fri, 15 Sep 2023 18:21:57 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D55ED3858416 for ; Fri, 15 Sep 2023 08:21:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D55ED3858416 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694766111; bh=JdgYX8/GKZ3p7/PgbtCiqxwvBYBy6lBeMjSgtbaNZw8=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=cpo7s2KOLvrtcdjUF55X5N6Ma4p4CTal11saa9YJ1iyXv3lypbNXw+/vdxlA76XaS TJ/0vEA8yftE7ZPgSQsyJIt+Kk9ZzN3BDUn22IXWmW7N2GFGaRv+JLy26eTXcslSMm vdQ/TSkcArgIpZSKQdXpfv9C/dPIZr4suDc0rwjM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 2CD283858D35 for ; Fri, 15 Sep 2023 08:21:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2CD283858D35 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DE6991FB for ; Fri, 15 Sep 2023 01:21:58 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4E33A3F67D for ; Fri, 15 Sep 2023 01:21:21 -0700 (PDT) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH] aarch64: Fix loose ldpstp check [PR111411] Date: Fri, 15 Sep 2023 09:21:20 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-24.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" aarch64_operands_ok_for_ldpstp contained the code: /* One of the memory accesses must be a mempair operand. If it is not the first one, they need to be swapped by the peephole. */ if (!aarch64_mem_pair_operand (mem_1, GET_MODE (mem_1)) && !aarch64_mem_pair_operand (mem_2, GET_MODE (mem_2))) return false; But the requirement isn't just that one of the accesses must be a valid mempair operand. It's that the lower access must be, since that's the access that will be used for the instruction operand. Tested on aarch64-linux-gnu & pushed. The patch applies cleanly to GCC 12 and 13, so I'll backport there next week. GCC 11 will need a bespoke fix if the problem shows up there, but I doubt it will. Richard gcc/ PR target/111411 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp): Require the lower memory access to a mem-pair operand. gcc/testsuite/ PR target/111411 * gcc.dg/rtl/aarch64/pr111411.c: New test. --- gcc/config/aarch64/aarch64.cc | 8 ++- gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c | 57 +++++++++++++++++++++ 2 files changed, 60 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 0962fc4f56e..7bb1161f943 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -26503,11 +26503,9 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, gcc_assert (known_eq (GET_MODE_SIZE (GET_MODE (mem_1)), GET_MODE_SIZE (GET_MODE (mem_2)))); - /* One of the memory accesses must be a mempair operand. - If it is not the first one, they need to be swapped by the - peephole. */ - if (!aarch64_mem_pair_operand (mem_1, GET_MODE (mem_1)) - && !aarch64_mem_pair_operand (mem_2, GET_MODE (mem_2))) + /* The lower memory access must be a mem-pair operand. */ + rtx lower_mem = reversed ? mem_2 : mem_1; + if (!aarch64_mem_pair_operand (lower_mem, GET_MODE (lower_mem))) return false; if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1))) diff --git a/gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c b/gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c new file mode 100644 index 00000000000..ad07e9c6c89 --- /dev/null +++ b/gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c @@ -0,0 +1,57 @@ +/* { dg-do compile { target aarch64*-*-* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O -fdisable-rtl-postreload -fpeephole2 -fno-schedule-fusion" } */ + +extern int data[]; + +void __RTL (startwith ("ira")) foo (void *ptr) +{ + (function "foo" + (param "ptr" + (DECL_RTL (reg/v:DI <0> [ ptr ])) + (DECL_RTL_INCOMING (reg/v:DI x0 [ ptr ])) + ) ;; param "ptr" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) + (insn 4 (set (reg:DI <0>) (reg:DI x0))) + (insn 5 (set (reg:DI <1>) + (plus:DI (reg:DI <0>) (const_int 768)))) + (insn 6 (set (mem:SI (plus:DI (reg:DI <0>) + (const_int 508)) [1 &data+508 S4 A4]) + (const_int 0))) + (insn 7 (set (mem:SI (plus:DI (reg:DI <1>) + (const_int -256)) [1 &data+512 S4 A4]) + (const_int 0))) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain + ) ;; function +} + +void __RTL (startwith ("ira")) bar (void *ptr) +{ + (function "bar" + (param "ptr" + (DECL_RTL (reg/v:DI <0> [ ptr ])) + (DECL_RTL_INCOMING (reg/v:DI x0 [ ptr ])) + ) ;; param "ptr" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) + (insn 4 (set (reg:DI <0>) (reg:DI x0))) + (insn 5 (set (reg:DI <1>) + (plus:DI (reg:DI <0>) (const_int 768)))) + (insn 6 (set (mem:SI (plus:DI (reg:DI <1>) + (const_int -256)) [1 &data+512 S4 A4]) + (const_int 0))) + (insn 7 (set (mem:SI (plus:DI (reg:DI <0>) + (const_int 508)) [1 &data+508 S4 A4]) + (const_int 0))) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain + ) ;; function +}