diff --git a/gcc/config/aarch64/aarch64-early-ra.cc b/gcc/config/aarch64/aarch64-early-ra.cc
index bbd84686e13..0db8ea24389 100644
--- a/gcc/config/aarch64/aarch64-early-ra.cc
+++ b/gcc/config/aarch64/aarch64-early-ra.cc
@@ -1062,8 +1062,9 @@ is_stride_candidate (rtx_insn *insn)
     return false;
 
   auto stride_type = get_attr_stride_type (insn);
-  return (stride_type == STRIDE_TYPE_LD1_CONSECUTIVE
-	  || stride_type == STRIDE_TYPE_ST1_CONSECUTIVE);
+  return (TARGET_STREAMING_SME2
+	  && (stride_type == STRIDE_TYPE_LD1_CONSECUTIVE
+	      || stride_type == STRIDE_TYPE_ST1_CONSECUTIVE));
 }
 
 // Go through the constraints of INSN, which has already been extracted,
@@ -3213,9 +3214,9 @@ early_ra::maybe_convert_to_strided_access (rtx_insn *insn)
   auto stride_type = get_attr_stride_type (insn);
   rtx pat = PATTERN (insn);
   rtx op;
-  if (stride_type == STRIDE_TYPE_LD1_CONSECUTIVE)
+  if (TARGET_STREAMING_SME2 && stride_type == STRIDE_TYPE_LD1_CONSECUTIVE)
     op = SET_DEST (pat);
-  else if (stride_type == STRIDE_TYPE_ST1_CONSECUTIVE)
+  else if (TARGET_STREAMING_SME2 && stride_type == STRIDE_TYPE_ST1_CONSECUTIVE)
     op = XVECEXP (SET_SRC (pat), 0, 1);
   else
     return false;
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
index 5cc32aa8871..9e8aad957d5 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
@@ -226,40 +226,53 @@ DEF_SVE_FUNCTION (svpsel_lane, select_pred, all_pred_count, none)
 DEF_SVE_FUNCTION (svrevd, unary, all_data, mxz)
 #undef REQUIRED_EXTENSIONS
 
-#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2)
-DEF_SVE_FUNCTION_GS (svadd, binary_single, all_integer, x24, none)
+#define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2p1, AARCH64_FL_SME2)
 DEF_SVE_FUNCTION (svbfmlslb, ternary_bfloat_opt_n, s_float, none)
 DEF_SVE_FUNCTION (svbfmlslb_lane, ternary_bfloat_lane, s_float, none)
 DEF_SVE_FUNCTION (svbfmlslt, ternary_bfloat_opt_n, s_float, none)
 DEF_SVE_FUNCTION (svbfmlslt_lane, ternary_bfloat_lane, s_float, none)
 DEF_SVE_FUNCTION (svclamp, clamp, all_float, none)
-DEF_SVE_FUNCTION_GS (svclamp, clamp, all_arith, x24, none)
 DEF_SVE_FUNCTION (svcntp, count_pred_c, all_count, none)
-DEF_SVE_FUNCTION_GS (svcvt, unary_convertxn, cvt_h_s_float, x2, none)
-DEF_SVE_FUNCTION_GS (svcvt, unary_convertxn, cvt_s_s, x24, none)
-DEF_SVE_FUNCTION_GS (svcvtn, unary_convertxn, cvt_h_s_float, x2, none)
 DEF_SVE_FUNCTION (svdot, ternary_qq_opt_n_or_011, s_narrow_fsu, none)
 DEF_SVE_FUNCTION (svdot_lane, ternary_qq_or_011_lane, s_narrow_fsu, none)
 DEF_SVE_FUNCTION_GS (svld1, load, all_data, x24, implicit)
 DEF_SVE_FUNCTION_GS (svldnt1, load, all_data, x24, implicit)
+DEF_SVE_FUNCTION_GS (svpext_lane, extract_pred, all_count, x12, none)
+DEF_SVE_FUNCTION (svptrue, inherent, all_count, none)
+DEF_SVE_FUNCTION_GS (svqcvtn, unary_convertxn, qcvt_x2, x2, none)
+DEF_SVE_FUNCTION_GS (svqrshrn, shift_right_imm_narrowxn, qrshr_x2, x2, none)
+DEF_SVE_FUNCTION_GS (svqrshrun, shift_right_imm_narrowxn, qrshru_x2, x2, none)
+DEF_SVE_FUNCTION_GS (svst1, storexn, all_data, x24, implicit)
+DEF_SVE_FUNCTION_GS (svstnt1, storexn, all_data, x24, implicit)
+DEF_SVE_FUNCTION_GS (svwhilege, compare_scalar, while_x, x2, none)
+DEF_SVE_FUNCTION (svwhilege, compare_scalar_count, while_x_c, none)
+DEF_SVE_FUNCTION_GS (svwhilegt, compare_scalar, while_x, x2, none)
+DEF_SVE_FUNCTION (svwhilegt, compare_scalar_count, while_x_c, none)
+DEF_SVE_FUNCTION_GS (svwhilele, compare_scalar, while_x, x2, none)
+DEF_SVE_FUNCTION (svwhilele, compare_scalar_count, while_x_c, none)
+DEF_SVE_FUNCTION_GS (svwhilelt, compare_scalar, while_x, x2, none)
+DEF_SVE_FUNCTION (svwhilelt, compare_scalar_count, while_x_c, none)
+#undef REQUIRED_EXTENSIONS
+
+#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2)
+DEF_SVE_FUNCTION_GS (svadd, binary_single, all_integer, x24, none)
+DEF_SVE_FUNCTION_GS (svclamp, clamp, all_arith, x24, none)
+DEF_SVE_FUNCTION_GS (svcvt, unary_convertxn, cvt_h_s_float, x2, none)
+DEF_SVE_FUNCTION_GS (svcvt, unary_convertxn, cvt_s_s, x24, none)
+DEF_SVE_FUNCTION_GS (svcvtn, unary_convertxn, cvt_h_s_float, x2, none)
 DEF_SVE_FUNCTION_GS (svmax, binary_opt_single_n, all_arith, x24, none)
 DEF_SVE_FUNCTION_GS (svmaxnm, binary_opt_single_n, all_float, x24, none)
 DEF_SVE_FUNCTION_GS (svmin, binary_opt_single_n, all_arith, x24, none)
 DEF_SVE_FUNCTION_GS (svminnm, binary_opt_single_n, all_float, x24, none)
-DEF_SVE_FUNCTION_GS (svpext_lane, extract_pred, all_count, x12, none)
-DEF_SVE_FUNCTION (svptrue, inherent, all_count, none)
 DEF_SVE_FUNCTION_GS (svqcvt, unary_convertxn, qcvt_x2, x2, none)
 DEF_SVE_FUNCTION_GS (svqcvt, unary_convertxn, qcvt_x4, x4, none)
-DEF_SVE_FUNCTION_GS (svqcvtn, unary_convertxn, qcvt_x2, x2, none)
 DEF_SVE_FUNCTION_GS (svqcvtn, unary_convertxn, qcvt_x4, x4, none)
 DEF_SVE_FUNCTION_GS (svqdmulh, binary_opt_single_n, all_signed, x24, none)
 DEF_SVE_FUNCTION_GS (svqrshr, shift_right_imm_narrowxn, qrshr_x2, x2, none)
 DEF_SVE_FUNCTION_GS (svqrshr, shift_right_imm_narrowxn, qrshr_x4, x4, none)
-DEF_SVE_FUNCTION_GS (svqrshrn, shift_right_imm_narrowxn, qrshr_x2, x2, none)
 DEF_SVE_FUNCTION_GS (svqrshrn, shift_right_imm_narrowxn, qrshr_x4, x4, none)
 DEF_SVE_FUNCTION_GS (svqrshru, shift_right_imm_narrowxn, qrshru_x2, x2, none)
 DEF_SVE_FUNCTION_GS (svqrshru, shift_right_imm_narrowxn, qrshru_x4, x4, none)
-DEF_SVE_FUNCTION_GS (svqrshrun, shift_right_imm_narrowxn, qrshru_x2, x2, none)
 DEF_SVE_FUNCTION_GS (svqrshrun, shift_right_imm_narrowxn, qrshru_x4, x4, none)
 DEF_SVE_FUNCTION_GS (svrinta, unaryxn, s_float, x24, none)
 DEF_SVE_FUNCTION_GS (svrintm, unaryxn, s_float, x24, none)
@@ -267,19 +280,9 @@ DEF_SVE_FUNCTION_GS (svrintn, unaryxn, s_float, x24, none)
 DEF_SVE_FUNCTION_GS (svrintp, unaryxn, s_float, x24, none)
 DEF_SVE_FUNCTION_GS (svrshl, binary_int_opt_single_n, all_integer, x24, none)
 DEF_SVE_FUNCTION_GS (svsel, binaryxn, all_data, x24, implicit)
-DEF_SVE_FUNCTION_GS (svst1, storexn, all_data, x24, implicit)
-DEF_SVE_FUNCTION_GS (svstnt1, storexn, all_data, x24, implicit)
 DEF_SVE_FUNCTION_GS (svunpk, unary_convertxn, bhs_widen, x24, none)
 DEF_SVE_FUNCTION_GS (svuzp, unaryxn, all_data, x24, none)
 DEF_SVE_FUNCTION_GS (svuzpq, unaryxn, all_data, x24, none)
-DEF_SVE_FUNCTION_GS (svwhilege, compare_scalar, while_x, x2, none)
-DEF_SVE_FUNCTION (svwhilege, compare_scalar_count, while_x_c, none)
-DEF_SVE_FUNCTION_GS (svwhilegt, compare_scalar, while_x, x2, none)
-DEF_SVE_FUNCTION (svwhilegt, compare_scalar_count, while_x_c, none)
-DEF_SVE_FUNCTION_GS (svwhilele, compare_scalar, while_x, x2, none)
-DEF_SVE_FUNCTION (svwhilele, compare_scalar_count, while_x_c, none)
-DEF_SVE_FUNCTION_GS (svwhilelt, compare_scalar, while_x, x2, none)
-DEF_SVE_FUNCTION (svwhilelt, compare_scalar_count, while_x_c, none)
 DEF_SVE_FUNCTION_GS (svzip, unaryxn, all_data, x24, none)
 DEF_SVE_FUNCTION_GS (svzipq, unaryxn, all_data, x24, none)
 #undef REQUIRED_EXTENSIONS
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 3d92a2a454f..f89036c35f7 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -7222,7 +7222,7 @@ (define_insn "@aarch64_<sur>dot_prod_lane<SVE_FULL_SDI:mode><SVE_FULL_BHI:mode>"
 	  (match_operand:SVE_FULL_SDI 4 "register_operand")))]
   "TARGET_SVE
    && (<SVE_FULL_SDI:elem_bits> == <SVE_FULL_BHI:elem_bits> * 4
-       || (TARGET_STREAMING_SME2
+       || (TARGET_SVE2p1_OR_SME2
 	   && <SVE_FULL_SDI:elem_bits> == 32
 	   && <SVE_FULL_BHI:elem_bits> == 16))"
   {@ [ cons: =0 , 1 , 2                           , 4 ; attrs: movprfx ]
@@ -7839,8 +7839,8 @@ (define_insn "@aarch64_sve_tmad<mode>"
 ;; - BFDOT (BF16)
 ;; - BFMLALB (BF16)
 ;; - BFMLALT (BF16)
-;; - BFMLSLB (SME2)
-;; - BFMLSLT (SME2)
+;; - BFMLSLB (SVE2p1, SME2)
+;; - BFMLSLT (SVE2p1, SME2)
 ;; - BFMMLA (BF16)
 ;; -------------------------------------------------------------------------
 
@@ -7851,7 +7851,7 @@ (define_insn "@aarch64_sve_<sve_fp_op>vnx4sf"
 	   (match_operand:VNx8BF 2 "register_operand")
 	   (match_operand:VNx8BF 3 "register_operand")]
 	  SVE_BFLOAT_TERNARY_LONG))]
-  "TARGET_SVE_BF16"
+  ""
   {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
      [ w        , 0 , w , w ; *              ] <sve_fp_op>\t%0.s, %2.h, %3.h
      [ ?&w      , w , w , w ; yes            ] movprfx\t%0, %1\;<sve_fp_op>\t%0.s, %2.h, %3.h
@@ -7867,7 +7867,7 @@ (define_insn "@aarch64_sve_<sve_fp_op>_lanevnx4sf"
 	   (match_operand:VNx8BF 3 "register_operand")
 	   (match_operand:SI 4 "const_int_operand")]
 	  SVE_BFLOAT_TERNARY_LONG_LANE))]
-  "TARGET_SVE_BF16"
+  ""
   {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
      [ w        , 0 , w , y ; *              ] <sve_fp_op>\t%0.s, %2.h, %3.h[%4]
      [ ?&w      , w , w , y ; yes            ] movprfx\t%0, %1\;<sve_fp_op>\t%0.s, %2.h, %3.h[%4]
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index fd4bd42b6d9..61bae64955f 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -140,7 +140,7 @@ (define_insn "@aarch64_<optab><mode>"
 	  [(match_operand:VNx16BI 2 "register_operand" "Uph")
 	   (match_operand:SVE_FULLx24 1 "memory_operand" "m")]
 	  LD1_COUNT))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   "<optab><Vesize>\t%0, %K2/z, %1"
   [(set_attr "stride_type" "ld1_consecutive")]
 )
@@ -276,7 +276,7 @@ (define_insn "@aarch64_<optab><mode>"
 	   (match_operand:SVE_FULLx24 1 "aligned_register_operand" "Uw<vector_count>")
 	   (match_dup 0)]
 	  ST1_COUNT))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   "<optab><Vesize>\t%1, %K2, %0"
   [(set_attr "stride_type" "st1_consecutive")]
 )
@@ -370,7 +370,7 @@ (define_insn "@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>"
 (define_insn "@aarch64_sve_ptrue_c<BHSD_BITS>"
   [(set (match_operand:VNx16BI 0 "register_operand" "=Uph")
 	(unspec:VNx16BI [(const_int BHSD_BITS)] UNSPEC_PTRUE_C))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   "ptrue\t%K0.<bits_etype>"
 )
 
@@ -388,7 +388,7 @@ (define_insn "@aarch64_sve_pext<BHSD_BITS>"
 	   (match_operand:DI 2 "const_int_operand")
 	   (const_int BHSD_BITS)]
 	  UNSPEC_PEXT))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   "pext\t%0.<bits_etype>, %K1[%2]"
 )
 
@@ -399,7 +399,7 @@ (define_insn "@aarch64_sve_pext<BHSD_BITS>x2"
 	   (match_operand:DI 2 "const_int_operand")
 	   (const_int BHSD_BITS)]
 	  UNSPEC_PEXTx2))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   "pext\t{%S0.<bits_etype>, %T0.<bits_etype>}, %K1[%2]"
 )
 
@@ -451,7 +451,7 @@ (define_insn "@aarch64_sve_cntp_c<BHSD_BITS>"
 	   (match_operand:DI 2 "const_int_operand")
 	   (const_int BHSD_BITS)]
 	  UNSPEC_CNTP_C))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   "cntp\t%x0, %K1.<bits_etype>, vlx%2"
 )
 
@@ -1117,7 +1117,7 @@ (define_insn "@aarch64_sve_fclamp<mode>"
 	     UNSPEC_FMAXNM)
 	   (match_operand:SVE_FULL_F 3 "register_operand")]
 	  UNSPEC_FMINNM))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   {@ [cons: =0,  1, 2, 3; attrs: movprfx]
      [       w, %0, w, w; *             ] fclamp\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>
      [     ?&w,  w, w, w; yes           ] movprfx\t%0, %1\;fclamp\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>
@@ -1137,7 +1137,7 @@ (define_insn_and_split "*aarch64_sve_fclamp<mode>_x"
 	     UNSPEC_COND_FMAXNM)
 	   (match_operand:SVE_FULL_F 3 "register_operand")]
 	  UNSPEC_COND_FMINNM))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   {@ [cons: =0,  1, 2, 3; attrs: movprfx]
      [       w, %0, w, w; *             ] #
      [     ?&w,  w, w, w; yes           ] #
@@ -2039,7 +2039,7 @@ (define_insn "<sur>dot_prodvnx4sivnx8hi"
 	     (match_operand:VNx8HI 2 "register_operand")]
 	    DOTPROD)
 	  (match_operand:VNx4SI 3 "register_operand")))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
      [ w        , w , w , 0 ; *              ] <sur>dot\t%0.s, %1.h, %2.h
      [ ?&w      , w , w , w ; yes            ] movprfx\t%0, %3\;<sur>dot\t%0.s, %1.h, %2.h
@@ -2137,7 +2137,7 @@ (define_insn "aarch64_sve_fdotvnx4sfvnx8hf"
 	     (match_operand:VNx8HF 2 "register_operand")]
 	    UNSPEC_FDOT)
 	  (match_operand:VNx4SF 3 "register_operand")))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
      [ w        , w , w , 0 ; *              ] fdot\t%0.s, %1.h, %2.h
      [ ?&w      , w , w , w ; yes            ] movprfx\t%0, %3\;fdot\t%0.s, %1.h, %2.h
@@ -2155,7 +2155,7 @@ (define_insn "aarch64_fdot_prod_lanevnx4sfvnx8hf"
 	       UNSPEC_SVE_LANE_SELECT)]
 	    UNSPEC_FDOT)
 	  (match_operand:VNx4SF 4 "register_operand")))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   {@ [ cons: =0 , 1 , 2 , 4 ; attrs: movprfx ]
      [ w        , w , y , 0 ; *              ] fdot\t%0.s, %1.h, %2.h[%3]
      [ ?&w      , w , y , w ; yes            ] movprfx\t%0, %4\;fdot\t%0.s, %1.h, %2.h[%3]
@@ -2222,7 +2222,7 @@ (define_insn "@aarch64_sve_<optab><VNx8HI_ONLY:mode><VNx8SI_ONLY:mode>"
 	(unspec:VNx8HI_ONLY
 	  [(match_operand:VNx8SI_ONLY 1 "aligned_register_operand" "Uw<vector_count>")]
 	  SVE_QCVTxN))]
-  "TARGET_STREAMING_SME2"
+  ""
   "<optab>\t%0.h, %1"
 )
 
@@ -2336,6 +2336,14 @@ (define_insn "@aarch64_sve_<sve_int_op><mode>"
 ;; -------------------------------------------------------------------------
 ;; ---- [INT] Multi-vector narrowing right shifts
 ;; -------------------------------------------------------------------------
+;; Includes:
+;; - SQRSHR
+;; - SQRSHRN
+;; - SQRSHRU
+;; - SQRSHRUN
+;; - UQRSHR
+;; - UQRSHRN
+;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sve_<sve_int_op><mode>"
   [(set (match_operand:<VNARROW> 0 "register_operand" "=w")
@@ -2343,7 +2351,7 @@ (define_insn "@aarch64_sve_<sve_int_op><mode>"
 	  [(match_operand:SVE_FULL_SIx2_SDIx4 1 "register_operand" "Uw<vector_count>")
 	   (match_operand:DI 2 "const_int_operand")]
 	  SVE2_INT_SHIFT_IMM_NARROWxN))]
-  "TARGET_STREAMING_SME2"
+  "(<MODE>mode == VNx8SImode || TARGET_STREAMING_SME2)"
   "<sve_int_op>\t%0.<Ventype>, %1, #%2"
 )
 
@@ -3145,7 +3153,7 @@ (define_insn "@aarch64_sve_while<while_optab_cmp>_b<BHSD_BITS>_x2"
 	   (const_int BHSD_BITS)]
 	  SVE_WHILE_ORDER))
    (clobber (reg:CC_NZC CC_REGNUM))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   "while<cmp_op>\t{%S0.<bits_etype>, %T0.<bits_etype>}, %x1, %x2"
 )
 
@@ -3159,7 +3167,7 @@ (define_insn "@aarch64_sve_while<while_optab_cmp>_c<BHSD_BITS>"
 	   (match_operand:DI 3 "const_int_operand")]
 	  SVE_WHILE_ORDER))
    (clobber (reg:CC_NZC CC_REGNUM))]
-  "TARGET_STREAMING_SME2"
+  "TARGET_SVE2p1_OR_SME2"
   "while<cmp_op>\t%K0.<bits_etype>, %x1, %x2, vlx%3"
 )
 
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 404efa16c28..f07b2c49f0d 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -490,6 +490,10 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
    functions, since streaming mode itself implies SME.  */
 #define TARGET_SVE2p1_OR_SME (TARGET_SVE2p1 || TARGET_STREAMING)
 
+#define TARGET_SVE2p1_OR_SME2 \
+  ((TARGET_SVE2p1 || TARGET_STREAMING) \
+   && (TARGET_SME2 || TARGET_NON_STREAMING))
+
 /* Standard register usage.  */
 
 /* 31 64-bit general purpose registers R0-R30:
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index b8924cdc74b..73d674816f1 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -3050,19 +3050,19 @@ (define_int_iterator SVE_FP_BINARY_MULTI [UNSPEC_FMAX UNSPEC_FMAXNM
 					  UNSPEC_FMIN UNSPEC_FMINNM])
 
 (define_int_iterator SVE_BFLOAT_TERNARY_LONG
-  [UNSPEC_BFDOT
-   UNSPEC_BFMLALB
-   UNSPEC_BFMLALT
-   (UNSPEC_BFMLSLB "TARGET_STREAMING_SME2")
-   (UNSPEC_BFMLSLT "TARGET_STREAMING_SME2")
-   (UNSPEC_BFMMLA "TARGET_NON_STREAMING")])
+  [(UNSPEC_BFDOT "TARGET_SVE_BF16")
+   (UNSPEC_BFMLALB "TARGET_SVE_BF16")
+   (UNSPEC_BFMLALT "TARGET_SVE_BF16")
+   (UNSPEC_BFMLSLB "TARGET_SVE2p1_OR_SME2")
+   (UNSPEC_BFMLSLT "TARGET_SVE2p1_OR_SME2")
+   (UNSPEC_BFMMLA "TARGET_SVE_BF16 && TARGET_NON_STREAMING")])
 
 (define_int_iterator SVE_BFLOAT_TERNARY_LONG_LANE
-  [UNSPEC_BFDOT
-   UNSPEC_BFMLALB
-   UNSPEC_BFMLALT
-   (UNSPEC_BFMLSLB "TARGET_STREAMING_SME2")
-   (UNSPEC_BFMLSLT "TARGET_STREAMING_SME2")])
+  [(UNSPEC_BFDOT "TARGET_SVE_BF16")
+   (UNSPEC_BFMLALB "TARGET_SVE_BF16")
+   (UNSPEC_BFMLALT "TARGET_SVE_BF16")
+   (UNSPEC_BFMLSLB "TARGET_SVE2p1_OR_SME2")
+   (UNSPEC_BFMLSLT "TARGET_SVE2p1_OR_SME2")])
 
 (define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV
 					UNSPEC_IORV
@@ -3338,12 +3338,13 @@ (define_int_iterator SVE2_INT_SHIFT_IMM_NARROWT [UNSPEC_RSHRNT
 						 UNSPEC_UQRSHRNT
 						 UNSPEC_UQSHRNT])
 
-(define_int_iterator SVE2_INT_SHIFT_IMM_NARROWxN [UNSPEC_SQRSHR
-						  UNSPEC_SQRSHRN
-						  UNSPEC_SQRSHRU
-						  UNSPEC_SQRSHRUN
-						  UNSPEC_UQRSHR
-						  UNSPEC_UQRSHRN])
+(define_int_iterator SVE2_INT_SHIFT_IMM_NARROWxN
+  [(UNSPEC_SQRSHR "TARGET_STREAMING_SME2")
+   (UNSPEC_SQRSHRN "TARGET_SVE2p1_OR_SME2")
+   (UNSPEC_SQRSHRU "TARGET_STREAMING_SME2")
+   (UNSPEC_SQRSHRUN "TARGET_SVE2p1_OR_SME2")
+   (UNSPEC_UQRSHR "TARGET_STREAMING_SME2")
+   (UNSPEC_UQRSHRN "TARGET_SVE2p1_OR_SME2")])
 
 (define_int_iterator SVE2_INT_SHIFT_INSERT [UNSPEC_SLI UNSPEC_SRI])
 
@@ -3488,9 +3489,12 @@ (define_int_iterator SVE2_PMULL [UNSPEC_PMULLB UNSPEC_PMULLT])
 
 (define_int_iterator SVE2_PMULL_PAIR [UNSPEC_PMULLB_PAIR UNSPEC_PMULLT_PAIR])
 
-(define_int_iterator SVE_QCVTxN [UNSPEC_SQCVT UNSPEC_SQCVTN
-				 UNSPEC_SQCVTU UNSPEC_SQCVTUN
-				 UNSPEC_UQCVT UNSPEC_UQCVTN])
+(define_int_iterator SVE_QCVTxN [(UNSPEC_SQCVT "TARGET_STREAMING_SME2")
+				 (UNSPEC_SQCVTN "TARGET_SVE2p1_OR_SME2")
+				 (UNSPEC_SQCVTU "TARGET_STREAMING_SME2")
+				 (UNSPEC_SQCVTUN "TARGET_SVE2p1_OR_SME2")
+				 (UNSPEC_UQCVT "TARGET_STREAMING_SME2")
+				 (UNSPEC_UQCVTN "TARGET_SVE2p1_OR_SME2")])
 
 (define_int_iterator SVE2_SFx24_UNARY [UNSPEC_FRINTA UNSPEC_FRINTM
 				       UNSPEC_FRINTN UNSPEC_FRINTP])
