diff --git a/gcc/ChangeLog.NPS400 b/gcc/ChangeLog.NPS400
index 286f2dd..0281640 100644
--- a/gcc/ChangeLog.NPS400
+++ b/gcc/ChangeLog.NPS400
@@ -1,3 +1,14 @@
+2016-02-02  Joern Rennecke  <joern.rennecke@embecosm.com>
+	    Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* config/arc/arc.h (ARC_NPS400): Define if not already defined.
+	(UNALIGNED_ACCESS_DEFAULT): Define, if not already defined.
+	(STRICT_ALIGNMENT): Make use of unaligned_access var.
+	* config/arc/arc.c (arc_expand_movmem): Take STRICT_ALIGNMENT into
+	account.
+	* config/arc/arc.opt: (munaligned-access): New option.
+	* config/arc/t-nps400: Add munaligned-access to the multilib list.
+
 2016-02-01  Andrew Burgess  <andrew.burgess@embecosm.com>
 
        * config.gcc: Add support for arc*-mellanox-* nps400 targets.
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index d60db50..35bb44a 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -7137,7 +7137,7 @@ arc_expand_movmem (rtx *operands)
   HOST_WIDE_INT size;
   int align = INTVAL (operands[3]);
   unsigned n_pieces;
-  int piece = align;
+  int piece = STRICT_ALIGNMENT ? align : 4;
   rtx store[2];
   rtx tmpx[2];
   int i;
@@ -7146,7 +7146,7 @@ arc_expand_movmem (rtx *operands)
     return false;
   size = INTVAL (operands[2]);
   /* move_by_pieces_ninsns is static, so we can't use it.  */
-  if (align >= 4)
+  if (align >= 4 || !STRICT_ALIGNMENT)
     {
       if (TARGET_LL64)
 	n_pieces = (size + 4) / 8U + ((size >> 1) & 1) + (size & 1);
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 21c049f..1cb59ec 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -62,6 +62,10 @@ along with GCC; see the file COPYING3.  If not see
 #undef ASM_APP_OFF
 #undef CC1_SPEC
 
+#ifndef ARC_NPS400
+#define ARC_NPS400 0
+#endif
+
 /* Names to predefine in the preprocessor for this target machine.  */
 #define TARGET_CPU_CPP_BUILTINS()	\
  do {					\
@@ -309,6 +313,10 @@ along with GCC; see the file COPYING3.  If not see
 #define MULTILIB_DEFAULTS { "mARC700" }
 #endif
 
+#ifndef UNALIGNED_ACCESS_DEFAULT
+#define UNALIGNED_ACCESS_DEFAULT 0
+#endif
+
 /* Target machine storage layout.  */
 
 /* We want zero_extract to mean the same
@@ -416,10 +424,13 @@ if (GET_MODE_CLASS (MODE) == MODE_INT		\
 
 /* Set this nonzero if move instructions will actually fail to work
    when given unaligned data.  */
-/* On the ARC the lower address bits are masked to 0 as necessary.  The chip
-   won't croak when given an unaligned address, but the insn will still fail
-   to produce the correct result.  */
-#define STRICT_ALIGNMENT 1
+/* On most ARC cores the lower address bits are masked to 0 as necessary,
+   the chip won't croak when given an unaligned address, but the insn will
+   still fail to produce the correct result.  */
+/* The NPS400 ARC variant supports unaligned access.  Although not without
+   cost, this is still fast enough that we can justify keeping
+   SLOW_UNALIGNED_ACCESS off.  */
+#define STRICT_ALIGNMENT (!unaligned_access)
 
 /* Layout of source language data types.  */
 
diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index 2227b75..f8e062c 100644
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -456,3 +456,7 @@ Enum(arc_fpu) String(fpus_all) Value(FPU_SP | FPU_SC | FPU_SF | FPU_SD)
 
 EnumValue
 Enum(arc_fpu) String(fpud_all) Value(FPU_SP | FPU_SC | FPU_SF | FPU_SD | FPU_DP | FPU_DC | FPU_DF | FPU_DD)
+
+munaligned-access
+Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT) Condition(ARC_NPS400)
+Enable unaligned word and halfword accesses to packed data.
diff --git a/gcc/config/arc/t-nps400 b/gcc/config/arc/t-nps400
index e332e24..2d96b78 100644
--- a/gcc/config/arc/t-nps400
+++ b/gcc/config/arc/t-nps400
@@ -18,4 +18,4 @@
 # with GCC; see the file COPYING3.  If not see
 # <http://www.gnu.org/licenses/>.
 
-MULTILIB_OPTIONS=
+MULTILIB_OPTIONS=munaligned-access
diff --git a/gcc/testsuite/ChangeLog.NPS400 b/gcc/testsuite/ChangeLog.NPS400
new file mode 100644
index 0000000..b49dc1a
--- /dev/null
+++ b/gcc/testsuite/ChangeLog.NPS400
@@ -0,0 +1,6 @@
+2016-02-03  Joern Rennecke  <joern.rennecke@embecosm.com>
+
+	* gcc.target/arc/setmem-1.c: New file.
+	* gcc.target/arc/setmem-2.c: New file.
+	* gcc.target/arc/setmem-3.c: New file.
+	* gcc.target/arc/setmem-4.c: New file.
diff --git a/gcc/testsuite/gcc.target/arc/setmem-1.c b/gcc/testsuite/gcc.target/arc/setmem-1.c
new file mode 100644
index 0000000..926974e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/setmem-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target arc*-mellanox-* } } */
+/* { dg-options "-O2 -munaligned-access" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+void
+f (char *d)
+{
+  static const char a[] = "abcdefghijklmnopqrstuvwxyz";
+  memcpy (d, a, 20);
+}
+/* { dg-final { scan-assembler-not "stb"  } } */
+/* { dg-final { scan-assembler-not "memcpy"  } } */
diff --git a/gcc/testsuite/gcc.target/arc/setmem-2.c b/gcc/testsuite/gcc.target/arc/setmem-2.c
new file mode 100644
index 0000000..a034fbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/setmem-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target arc*-mellanox-* } } */
+/* { dg-options "-O2 -munaligned-access" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+void
+f (char *d)
+{
+  static const char a[] =
+    {
+      'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+      'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't',
+      'u', 'v', 'w', 'x', 'y', 'z',
+    };
+  memcpy (d, a, 20);
+}
+/* { dg-final { scan-assembler-not "stb"  } } */
+/* { dg-final { scan-assembler-not "memcpy"  } } */
diff --git a/gcc/testsuite/gcc.target/arc/setmem-3.c b/gcc/testsuite/gcc.target/arc/setmem-3.c
new file mode 100644
index 0000000..660d924
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/setmem-3.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target arc*-mellanox-* } } */
+/* { dg-options "-O2 -munaligned-access" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+void
+f (char *d)
+{
+  const char a[26] = "abcdefghijklmnopqrstuvwxyz";
+  memcpy (d, a, 20);
+}
+/* { dg-final { scan-assembler-not "stb"  } } */
+/* { dg-final { scan-assembler-not "memcpy"  } } */
diff --git a/gcc/testsuite/gcc.target/arc/setmem-4.c b/gcc/testsuite/gcc.target/arc/setmem-4.c
new file mode 100644
index 0000000..b5c1ee6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/setmem-4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target arc*-mellanox-* } } */
+/* { dg-options "-O2 -munaligned-access" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+void
+f (char *d)
+{
+  const char a[26] =
+    {
+      'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+      'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't',
+      'u', 'v', 'w', 'x', 'y', 'z',
+    };
+  memcpy (d, a, 20);
+}
+/* { dg-final { scan-assembler-not "stb" } } */
+/* { dg-final { scan-assembler-not "memcpy" } } */
