From patchwork Thu Jul 7 02:26:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 1653269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=p7iyS4LD; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LdgKS4bWNz9s09 for ; Thu, 7 Jul 2022 12:27:07 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7A7223858C39 for ; Thu, 7 Jul 2022 02:27:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7A7223858C39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1657160825; bh=uCx+xhWtMQ51jVHZ+e9G4Yqm4jcrw47kjOHdjmQQP0Y=; h=Subject:To:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=p7iyS4LDzWXpXPdE5rxrPKPL2BwwyJDvDmfyWq6CpjAqVYGiSH61blSuwjNpwO0gM j+XgBPVKBygkXVDutk4cAvHTXkLH9x2Zi+bvjiv7wWpbNahcaoXl3nj/M/xqOr3xbO Vu7DzbECTDih0ZuFbStwMoCK7XP0y0t+fCfZBlE8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 9794E3858C54 for ; Thu, 7 Jul 2022 02:26:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9794E3858C54 Received: from [IPv6:240e:358:1139:6500:dc73:854d:832e:4] (unknown [IPv6:240e:358:1139:6500:dc73:854d:832e:4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384)) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 1EE64669E1; Wed, 6 Jul 2022 22:26:40 -0400 (EDT) Message-ID: Subject: [PATCH 1/2] loongarch: add alternatives for idiv insns to improve code generation To: gcc-patches@gcc.gnu.org Date: Thu, 07 Jul 2022 10:26:37 +0800 In-Reply-To: <535ed6eaa19df38309a773f9bf2542c65f715b6b.camel@xry111.site> References: <535ed6eaa19df38309a773f9bf2542c65f715b6b.camel@xry111.site> User-Agent: Evolution 3.44.3 MIME-Version: 1.0 X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_PDS_OTHER_BAD_TLD, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Cc: Chenghua Xu , Lulu Cheng , Wang Xuerui Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Currently in the description of LoongArch integer division instructions, the output is marked as earlyclobbered ('&'). It's necessary when loongarch_check_zero_div_p() because clobbering operand 2 (divisor) will make the checking for zero divisor impossible. But, for -mno-check-zero-division (the default of GCC >= 12.2 for optimized code), the output is not earlyclobbered at all. And, the read of operand 1 only occurs before clobbering the output. So we make three alternatives for an idiv instruction: * (=r,r,r): For -mno-check-zero-division. * (=&r,r,r): For -mcheck-zero-division. * (=&r,0,r): For -mcheck-zero-division, to explicitly allow patterns like "div.d $a0, $a0, $a1". gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_check_zero_div_p): Remove static, for use in the machine description file. * config/loongarch/loongarch-protos.h: (loongarch_check_zero_div_p): Add prototype. * config/loongarch/loongarch.md (enabled): New attr. (*3): Add (=r,r,r) and (=&r,0,r) alternatives for idiv. Conditionally enable the alternatives using loongarch_check_zero_div_p. (di3_fake): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/div-1.c: New test. * gcc.target/loongarch/div-2.c: New test. * gcc.target/loongarch/div-3.c: New test. --- gcc/config/loongarch/loongarch-protos.h | 1 + gcc/config/loongarch/loongarch.cc | 2 +- gcc/config/loongarch/loongarch.md | 28 +++++++++++++++------- gcc/testsuite/gcc.target/loongarch/div-1.c | 9 +++++++ gcc/testsuite/gcc.target/loongarch/div-2.c | 9 +++++++ gcc/testsuite/gcc.target/loongarch/div-3.c | 9 +++++++ 6 files changed, 49 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/div-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/div-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/div-3.c diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h index 2144c2421ed..2287fd3763c 100644 --- a/gcc/config/loongarch/loongarch-protos.h +++ b/gcc/config/loongarch/loongarch-protos.h @@ -130,6 +130,7 @@ extern bool loongarch_symbol_binds_local_p (const_rtx); extern const char *current_section_name (void); extern unsigned int current_section_flags (void); extern bool loongarch_use_ins_ext_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); +extern bool loongarch_check_zero_div_p (void); union loongarch_gen_fn_ptrs { diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index d72b256df51..bc56282c9a7 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -2104,7 +2104,7 @@ loongarch_load_store_insns (rtx mem, rtx_insn *insn) /* Return true if we need to trap on division by zero. */ -static bool +bool loongarch_check_zero_div_p (void) { /* if -m[no-]check-zero-division is given explicitly. */ diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index d3c809e25f3..b002eb2ac22 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -110,6 +110,8 @@ (define_constants ;; ;; .................... +(define_attr "enabled" "no,yes" (const_string "yes")) + (define_attr "got" "unset,load" (const_string "unset")) @@ -763,26 +765,36 @@ (define_expand "3" }) (define_insn "*3" - [(set (match_operand:GPR 0 "register_operand" "=&r") - (any_div:GPR (match_operand:GPR 1 "register_operand" "r") - (match_operand:GPR 2 "register_operand" "r")))] + [(set (match_operand:GPR 0 "register_operand" "=r,&r,&r") + (any_div:GPR (match_operand:GPR 1 "register_operand" "r,r,0") + (match_operand:GPR 2 "register_operand" "r,r,r")))] "" { return loongarch_output_division (".\t%0,%1,%2", operands); } [(set_attr "type" "idiv") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "enabled") + (if_then_else + (match_test "!!which_alternative == loongarch_check_zero_div_p()") + (const_string "yes") + (const_string "no")))]) (define_insn "di3_fake" - [(set (match_operand:SI 0 "register_operand" "=&r") - (any_div:SI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "r")))] + [(set (match_operand:SI 0 "register_operand" "=r,&r,&r") + (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") + (match_operand:DI 2 "register_operand" "r,r,r")))] "" { return loongarch_output_division (".w\t%0,%1,%2", operands); } [(set_attr "type" "idiv") - (set_attr "mode" "SI")]) + (set_attr "mode" "SI") + (set (attr "enabled") + (if_then_else + (match_test "!!which_alternative == loongarch_check_zero_div_p()") + (const_string "yes") + (const_string "no")))]) ;; Floating point multiply accumulate instructions. diff --git a/gcc/testsuite/gcc.target/loongarch/div-1.c b/gcc/testsuite/gcc.target/loongarch/div-1.c new file mode 100644 index 00000000000..b1683f8535f --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/div-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcheck-zero-division" } */ +/* { dg-final { scan-assembler "div.\[wd\]\t\\\$r4,\\\$r4,\\\$r5" } } */ + +long +div(long a, long b) +{ + return a / b; +} diff --git a/gcc/testsuite/gcc.target/loongarch/div-2.c b/gcc/testsuite/gcc.target/loongarch/div-2.c new file mode 100644 index 00000000000..4c2beb5b930 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/div-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-check-zero-division" } */ +/* { dg-final { scan-assembler "div.\[wd\]\t\\\$r4,\\\$r5,\\\$r4" } } */ + +long +div(long a, long b) +{ + return b / a; +} diff --git a/gcc/testsuite/gcc.target/loongarch/div-3.c b/gcc/testsuite/gcc.target/loongarch/div-3.c new file mode 100644 index 00000000000..d25969263f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/div-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcheck-zero-division" } */ +/* { dg-final { scan-assembler-not "div.\[wd\]\t\\\$r4,\\\$r5,\\\$r4" } } */ + +long +div(long a, long b) +{ + return b / a; +}