Message ID | ef5944f4-28b5-1fe0-26b8-a348ea56d045@linux.ibm.com |
---|---|
State | New |
Headers | show |
Series | [v5,1/4] rs6000: Enable REE pass by default | expand |
Hi! On Tue, May 16, 2023 at 11:45:28AM +0530, Ajit Agarwal wrote: > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -12455,8 +12455,8 @@ Attempt to remove redundant extension instructions. This is especially > helpful for the x86-64 architecture, which implicitly zero-extends in 64-bit > registers after writing to their lower 32-bit half. > > -Enabled for Alpha, AArch64 and x86 at levels @option{-O2}, > -@option{-O3}, @option{-Os}. > +Enabled for Alpha, AArch64, RS/6000, RISC-V, SPARC, h83000 and x86 at levels > +@option{-O2}, @option{-O3}, @option{-Os}. Please don't mention RS/6000, we don't support that anymore. The architecture we do support is called Power or PowerPC; the target triplets are powerpc*-*-*. rs6000-*-* might still somewhat work, but no one should use it anymore, and we probably should delete it. Please say PowerPC here. With that the patch is okay for trunk. Thank you! Segher
diff --git a/gcc/common/config/rs6000/rs6000-common.cc b/gcc/common/config/rs6000/rs6000-common.cc index 2140c442ba9..968db215028 100644 --- a/gcc/common/config/rs6000/rs6000-common.cc +++ b/gcc/common/config/rs6000/rs6000-common.cc @@ -34,6 +34,8 @@ static const struct default_options rs6000_option_optimization_table[] = { OPT_LEVELS_ALL, OPT_fsplit_wide_types_early, NULL, 1 }, /* Enable -fsched-pressure for first pass instruction scheduling. */ { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 }, + /* Enable -free for zero extension and sign extension elimination.*/ + { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, /* Enable -munroll-only-small-loops with -funroll-loops to unroll small loops at -O2 and above by default. */ { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 }, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b92b8576027..168fcc88b1d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12455,8 +12455,8 @@ Attempt to remove redundant extension instructions. This is especially helpful for the x86-64 architecture, which implicitly zero-extends in 64-bit registers after writing to their lower 32-bit half. -Enabled for Alpha, AArch64 and x86 at levels @option{-O2}, -@option{-O3}, @option{-Os}. +Enabled for Alpha, AArch64, RS/6000, RISC-V, SPARC, h83000 and x86 at levels +@option{-O2}, @option{-O3}, @option{-Os}. @opindex fno-lifetime-dse @opindex flifetime-dse