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Wed, 01 Dec 2021 09:01:31 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1B191SuO26935578 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 1 Dec 2021 09:01:28 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 520FDA4065; Wed, 1 Dec 2021 09:01:28 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 89693A407D; Wed, 1 Dec 2021 09:01:26 +0000 (GMT) Received: from [9.200.100.183] (unknown [9.200.100.183]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 1 Dec 2021 09:01:26 +0000 (GMT) Message-ID: Date: Wed, 1 Dec 2021 17:01:23 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.3.1 Content-Language: en-US To: gcc-patches Subject: [PATCH] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453] X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 3DMItu9aHqPnBOuhRBUgVogu8GCN-tkV X-Proofpoint-ORIG-GUID: qGaWZjBRMThYjl_ZUk6mBeucapWoBpum X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-30_10,2021-11-28_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2112010052 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: HAO CHEN GUI via Gcc-patches From: HAO CHEN GUI Reply-To: HAO CHEN GUI Cc: Bill Schmidt , David , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch modifies the combine pattern with a helper - change_pseudo_and_mask when recog fails. The helper converts a single pseudo to the pseudo AND with a mask if the outer operator is IOR/XOR/PLUS and the inner operator is ASHIFT/LSHIFTRT/AND. The conversion helps match shift + ior pattern. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Is this okay for trunk? Any recommendations? Thanks a lot. ChangeLog 2021-12-01 Haochen Gui gcc/ * combine.c (change_pseudo_and_mask): New. (recog_for_combine): If recog fails, try again with the pattern modified by change_pseudo_and_mask. gcc/testsuite/ * gcc.target/powerpc/20050603-3.c: Modify dump check conditions. * gcc.target/powerpc/rlwimi-2.c: Likewise. patch.diff diff --git a/gcc/combine.c b/gcc/combine.c index 03e9a780919..82ee3b2e9db 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -11539,6 +11539,37 @@ change_zero_ext (rtx pat) return changed; } +/* When the outer code of set_src is IOR/XOR/PLUS and the inner code is + ASHIFT/LSHIFTRT/AND, convert a pseudo to psuedo AND with a mask if its + nonzero_bits is less than its mode mask. The nonzero_bits in other pass + doesn't return the same value as it does in combine pass. */ +static bool +change_pseudo_and_mask (rtx pat) +{ + bool changed = false; + + rtx src = SET_SRC (pat); + if ((GET_CODE (src) == IOR + || GET_CODE (src) == XOR + || GET_CODE (src) == PLUS) + && (((GET_CODE (XEXP (src, 0)) == ASHIFT + || GET_CODE (XEXP (src, 0)) == LSHIFTRT + || GET_CODE (XEXP (src, 0)) == AND) + && REG_P (XEXP (src, 1))))) + { + rtx *reg = &XEXP (SET_SRC (pat), 1); + machine_mode mode = GET_MODE (*reg); + unsigned HOST_WIDE_INT nonzero = nonzero_bits (*reg, mode); + if (nonzero < GET_MODE_MASK (mode)) + { + rtx x = gen_rtx_AND (mode, *reg, GEN_INT (nonzero)); + SUBST (*reg, x); + changed = true; + } + } + return changed; +} + /* Like recog, but we receive the address of a pointer to a new pattern. We try to match the rtx that the pointer points to. If that fails, we may try to modify or replace the pattern, @@ -11586,7 +11617,14 @@ recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) } } else - changed = change_zero_ext (pat); + { + if (change_pseudo_and_mask (pat)) + { + maybe_swap_commutative_operands (SET_SRC (pat)); + changed = true; + } + changed |= change_zero_ext (pat); + } } else if (GET_CODE (pat) == PARALLEL) { diff --git a/gcc/testsuite/gcc.target/powerpc/20050603-3.c b/gcc/testsuite/gcc.target/powerpc/20050603-3.c index 4017d34f429..e628be11532 100644 --- a/gcc/testsuite/gcc.target/powerpc/20050603-3.c +++ b/gcc/testsuite/gcc.target/powerpc/20050603-3.c @@ -12,7 +12,7 @@ void rotins (unsigned int x) b.y = (x<<12) | (x>>20); } -/* { dg-final { scan-assembler-not {\mrlwinm} } } */ +/* { dg-final { scan-assembler-not {\mrlwinm} { target ilp32 } } } */ /* { dg-final { scan-assembler-not {\mrldic} } } */ /* { dg-final { scan-assembler-not {\mrot[lr]} } } */ /* { dg-final { scan-assembler-not {\ms[lr][wd]} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c index bafa371db73..ffb5f9e450f 100644 --- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c @@ -2,14 +2,14 @@ /* { dg-options "-O2" } */ /* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 14121 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 20217 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 21279 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mr} 643 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 7790 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5036 } } */