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[46.5.130.86]) by smtp.gmail.com with ESMTPSA id w22-20020a50fa96000000b0052a3aa50d72sm6704987edr.40.2023.08.30.05.22.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Aug 2023 05:22:13 -0700 (PDT) Message-ID: Date: Wed, 30 Aug 2023 14:22:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Content-Language: en-US To: gcc-patches , "richard.sandiford" Subject: [PATCH] expmed: Allow extract_bit_field via mem for low-precision modes. X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Robin Dapp via Gcc-patches From: Robin Dapp Reply-To: Robin Dapp Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, when looking at a riscv ICE in vect-live-6.c I noticed that we assume that the variable part (coeffs[1] * x1) of the to-be-extracted bit number in extract_bit_field_1 is a multiple of BITS_PER_UNIT. This means that bits_to_bytes_round_down and num_trailing_bits cannot handle e.g. extracting from a "VNx4BI"-mode vector which has 4-bit precision on riscv. This patch adds a special case for that situation and sets bytenum to zero as well as bitnum to its proper value. It works for the riscv case because in all other situations we can align to a byte boundary. If x1 were 3 for some reason, however, the above assertion would still fail. I don't think this can happen for riscv as we only ever double the number of chunks for larger vector sizes but not sure about the general case. If there's another, correct way to work around feel free to suggest. Bootstrap/testsuite on aarch64 and x86 is running but I would be surprised if there were any changes as riscv is the only target that uses modes with precision < 8. Regards Robin gcc/ChangeLog: * expmed.cc (extract_bit_field_1): Handle bitnum with variable part less than BITS_PER_UNIT. --- gcc/expmed.cc | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/gcc/expmed.cc b/gcc/expmed.cc index e22e43c8505..1b0119f9cfc 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -1858,8 +1858,22 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum, but is useful for things like vector booleans. */ if (MEM_P (op0) && !bitnum.is_constant ()) { - bytenum = bits_to_bytes_round_down (bitnum); - bitnum = num_trailing_bits (bitnum); + /* bits_to_bytes_round_down tries to align to a byte (BITS_PER_UNIT) + boundary and asserts that bitnum.coeffs[1] % BITS_PER_UNIT == 0. + For modes with precision < BITS_PER_UNIT this fails but we can + still extract from the first byte. */ + poly_uint16 prec = GET_MODE_PRECISION (outermode); + if (prec.coeffs[1] < BITS_PER_UNIT && bitnum.coeffs[1] < BITS_PER_UNIT) + { + bytenum = 0; + bitnum = bitnum.coeffs[0] & (BITS_PER_UNIT - 1); + } + else + { + bytenum = bits_to_bytes_round_down (bitnum); + bitnum = num_trailing_bits (bitnum); + } + poly_uint64 bytesize = bits_to_bytes_round_up (bitnum + bitsize); op0 = adjust_bitfield_address_size (op0, BLKmode, bytenum, bytesize); op0_mode = opt_scalar_int_mode ();