From patchwork Mon Nov 21 11:31:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 697212 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tMmdY3tYhz9rxv for ; Mon, 21 Nov 2016 22:31:29 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="xJInmji0"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :references:subject:to:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=OkKCbOmbOmaFTzI/b NGGEpMZ1aDBoGwc8aZh6DDec08/YSuwUXIOd2LUsa0SPCTGMiTiDgpXq6rQjptBy 7qQGSHgkZx9knL6nOBzW03im/1JIkNH3+OQLz4iLweZHbt1i9z0hv3aYrKH8NCy0 S6m+Kv1lCk4VC1ciFOX+vxnOVQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :references:subject:to:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=BxZCH40HfGuIxFmWzxYMgJI kGg8=; b=xJInmji0Zo7+Wp2xd7sg2wf2UGo+KdW39BuvHgo/hzhK+jjHkqO6Zui /sai+VZmOsprLmBU1HBq7EN907Cd7YLa/91pMIMdzd/6GMw6IWWm0L7uIPPHjM/V H42ovUCtVvNQkQ3st3dA0LOoPWOpsPAPFYCgOnsu8K7wYu1hyJOc= Received: (qmail 14052 invoked by alias); 21 Nov 2016 11:31:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14035 invoked by uid 89); 21 Nov 2016 11:31:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=coprocessor, 8.1, 8.2, Neon X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 Nov 2016 11:31:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ADD7128; Mon, 21 Nov 2016 03:31:05 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5FD3E3F220 for ; Mon, 21 Nov 2016 03:31:05 -0800 (PST) References: <84f81112-b7a6-b043-d62d-4c44ac5d8c6c@foss.arm.com> Subject: [arm-embedded] [PATCH, GCC/ARM] Make arm_feature_set agree with type of FL_* macros To: "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme X-Forwarded-Message-Id: <84f81112-b7a6-b043-d62d-4c44ac5d8c6c@foss.arm.com> Message-ID: Date: Mon, 21 Nov 2016 11:31:04 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <84f81112-b7a6-b043-d62d-4c44ac5d8c6c@foss.arm.com> X-IsSubscribed: yes Hi, We have decided to backport this patch to fix a type inconsistency for arm_feature_set to our embedded-6-branch. *** gcc/ChangeLog.arm *** 2016-11-18 Thomas Preud'homme Backport from mainline 2016-11-18 Thomas Preud'homme * config/arm/arm-protos.h (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32, FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E, FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM, FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV, FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT, FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST): Reindent comment, add final dot when missing and make value unsigned. (arm_feature_set): Use unsigned entries instead of unsigned long. Hi, I've rebased the patch to make arm_feature_set agree with type of FL_* macros on top of trunk rather than on top of the optional -mthumb patch. That involved doing the changes to gcc/config/arm/arm-protos.h rather than gcc/config/arm/arm-flags.h. I also took advantage of the fact that each line is changed to change the indentation to tabs and add dots in comments missing one. For reference, please find below the original patch description: Currently arm_feature_set is defined in gcc/config/arm/arm-flags as an array of 2 unsigned long. However, the flags stored in these two entries are (signed) int, being combinations of bits set via expression of the form 1 << bitno. This creates 3 issues: 1) undefined behavior when setting the msb (1 << 31) 2) undefined behavior when storing a flag with msb set (negative int) into one of the unsigned array entries (positive int) 3) waste of space since the top 32 bits of each entry is not used This patch changes the definition of FL_* macro to be unsigned int by using the form 1U << bitno instead and changes the definition of arm_feature_set to be an array of 2 unsigned (int) entries. *** gcc/ChangeLog *** 2016-10-15 Thomas Preud'homme * config/arm/arm-protos.h (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32, FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E, FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM, FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV, FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT, FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST): Reindent comment, add final dot when missing and make value unsigned. (arm_feature_set): Use unsigned entries instead of unsigned long. Bootstrapped on arm-linux-gnueabihf targeting Thumb-2 state. Is this ok for trunk? Best regards, Thomas On 14/11/16 18:56, Thomas Preudhomme wrote: > My apologize, I realized when trying to apply the patch that I wrote it on top > of the optional -mthumb patch instead of the reverse. I'll rebase it to not > screw up bisect. > > Best regards, > > Thomas > > On 14/11/16 14:47, Kyrill Tkachov wrote: >> >> On 14/11/16 14:07, Thomas Preudhomme wrote: >>> Hi, >>> >>> Currently arm_feature_set is defined in gcc/config/arm/arm-flags as an array >>> of 2 unsigned long. However, the flags stored in these two entries are >>> (signed) int, being combinations of bits set via expression of the form 1 << >>> bitno. This creates 3 issues: >>> >>> 1) undefined behavior when setting the msb (1 << 31) >>> 2) undefined behavior when storing a flag with msb set (negative int) into one >>> of the unsigned array entries (positive int) >>> 3) waste of space since the top 32 bits of each entry is not used >>> >>> This patch changes the definition of FL_* macro to be unsigned int by using >>> the form 1U << bitno instead and changes the definition of arm_feature_set to >>> be an array of 2 unsigned (int) entries. >>> >>> Bootstrapped on arm-linux-gnueabihf targeting Thumb-2 state. >>> >>> Is this ok for trunk? >>> >> >> Ok. >> Thanks, >> Kyrill >> >>> Best regards, >>> >>> Thomas >> diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 95bae5ef57ba4c433c0cce8e0c197959abdf887b..5cee7718554886982f535da2e9baa5015da609e4 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -351,50 +351,51 @@ extern bool arm_is_constant_pool_ref (rtx); /* Flags used to identify the presence of processor capabilities. */ /* Bit values used to identify processor capabilities. */ -#define FL_NONE (0) /* No flags. */ -#define FL_ANY (0xffffffff) /* All flags. */ -#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ -#define FL_ARCH3M (1 << 1) /* Extended multiply */ -#define FL_MODE26 (1 << 2) /* 26-bit mode support */ -#define FL_MODE32 (1 << 3) /* 32-bit mode support */ -#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ -#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ -#define FL_THUMB (1 << 6) /* Thumb aware */ -#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ -#define FL_STRONG (1 << 8) /* StrongARM */ -#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ -#define FL_XSCALE (1 << 10) /* XScale */ -/* spare (1 << 11) */ -#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds - media instructions. */ -#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ -#define FL_WBUF (1 << 14) /* Schedule for write buffer ops. - Note: ARM6 & 7 derivatives only. */ -#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ -#define FL_THUMB2 (1 << 16) /* Thumb-2. */ -#define FL_NOTM (1 << 17) /* Instructions not present in the 'M' - profile. */ -#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */ -#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ -#define FL_NEON (1 << 20) /* Neon instructions. */ -#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M - architecture. */ -#define FL_ARCH7 (1 << 22) /* Architecture 7. */ -#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */ -#define FL_ARCH8 (1 << 24) /* Architecture 8. */ -#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */ - -#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */ -#define FL_NO_VOLATILE_CE (1 << 27) /* No volatile memory in IT block. */ - -#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ -#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ -#define FL_ARCH6KZ (1 << 31) /* ARMv6KZ architecture. */ - -#define FL2_ARCH8_1 (1 << 0) /* Architecture 8.1. */ -#define FL2_ARCH8_2 (1 << 1) /* Architecture 8.2. */ -#define FL2_FP16INST (1 << 2) /* FP16 Instructions for ARMv8.2 and - later. */ +#define FL_NONE (0U) /* No flags. */ +#define FL_ANY (0xffffffffU) /* All flags. */ +#define FL_CO_PROC (1U << 0) /* Has external co-processor bus. */ +#define FL_ARCH3M (1U << 1) /* Extended multiply. */ +#define FL_MODE26 (1U << 2) /* 26-bit mode support. */ +#define FL_MODE32 (1U << 3) /* 32-bit mode support. */ +#define FL_ARCH4 (1U << 4) /* Architecture rel 4. */ +#define FL_ARCH5 (1U << 5) /* Architecture rel 5. */ +#define FL_THUMB (1U << 6) /* Thumb aware. */ +#define FL_LDSCHED (1U << 7) /* Load scheduling necessary. */ +#define FL_STRONG (1U << 8) /* StrongARM. */ +#define FL_ARCH5E (1U << 9) /* DSP extensions to v5. */ +#define FL_XSCALE (1U << 10) /* XScale. */ +/* spare (1U << 11) */ +#define FL_ARCH6 (1U << 12) /* Architecture rel 6. Adds + media instructions. */ +#define FL_VFPV2 (1U << 13) /* Vector Floating Point V2. */ +#define FL_WBUF (1U << 14) /* Schedule for write buffer ops. + Note: ARM6 & 7 derivatives only. */ +#define FL_ARCH6K (1U << 15) /* Architecture rel 6 K extensions. */ +#define FL_THUMB2 (1U << 16) /* Thumb-2. */ +#define FL_NOTM (1U << 17) /* Instructions not present in the 'M' + profile. */ +#define FL_THUMB_DIV (1U << 18) /* Hardware divide (Thumb mode). */ +#define FL_VFPV3 (1U << 19) /* Vector Floating Point V3. */ +#define FL_NEON (1U << 20) /* Neon instructions. */ +#define FL_ARCH7EM (1U << 21) /* Instructions present in the ARMv7E-M + architecture. */ +#define FL_ARCH7 (1U << 22) /* Architecture 7. */ +#define FL_ARM_DIV (1U << 23) /* Hardware divide (ARM mode). */ +#define FL_ARCH8 (1U << 24) /* Architecture 8. */ +#define FL_CRC32 (1U << 25) /* ARMv8 CRC32 instructions. */ +#define FL_SMALLMUL (1U << 26) /* Small multiply supported. */ +#define FL_NO_VOLATILE_CE (1U << 27) /* No volatile memory in IT block. */ + +#define FL_IWMMXT (1U << 29) /* XScale v2 or "Intel Wireless MMX + technology". */ +#define FL_IWMMXT2 (1U << 30) /* "Intel Wireless MMX2 + technology". */ +#define FL_ARCH6KZ (1U << 31) /* ARMv6KZ architecture. */ + +#define FL2_ARCH8_1 (1U << 0) /* Architecture 8.1. */ +#define FL2_ARCH8_2 (1U << 1) /* Architecture 8.2. */ +#define FL2_FP16INST (1U << 2) /* FP16 Instructions for ARMv8.2 and + later. */ /* Flags that only effect tuning, not available instructions. */ #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ @@ -436,7 +437,7 @@ extern bool arm_is_constant_pool_ref (rtx); typedef struct { - unsigned long cpu[2]; + unsigned cpu[2]; } arm_feature_set;