diff mbox series

test/rs6000: Add cases to cover vector multiply

Message ID e39677a7-ee5e-a685-0dc1-f3591acc4c7d@linux.ibm.com
State New
Headers show
Series test/rs6000: Add cases to cover vector multiply | expand

Commit Message

Kewen.Lin July 7, 2021, 9:02 a.m. UTC 
Hi,

This patch is to add test cases to check if vectorizer
can exploit vector multiply instrutions on Power, some
of them are supported since Power8, the other are newly
introduced by Power10.

Is it ok for trunk?

BR,
Kewen
-----
gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/mul-vectorize-1.c: New test.
	* gcc.target/powerpc/mul-vectorize-2.c: New test.
---
 .../gcc.target/powerpc/mul-vectorize-1.c      | 27 +++++++++++++++++++
 .../gcc.target/powerpc/mul-vectorize-2.c      | 27 +++++++++++++++++++
 2 files changed, 54 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/mul-vectorize-2.c

Comments

Segher Boessenkool July 7, 2021, 3:32 p.m. UTC | #1 
Hi!

On Wed, Jul 07, 2021 at 05:02:42PM +0800, Kewen.Lin wrote:
> This patch is to add test cases to check if vectorizer
> can exploit vector multiply instrutions on Power, some
> of them are supported since Power8, the other are newly
> introduced by Power10.

Okay for trunk.  Thank you!


Segher
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c
new file mode 100644
index 00000000000..ba01d5cec8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c
@@ -0,0 +1,27 @@ 
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */
+
+/* Test vectorizer can exploit ISA 2.07 instruction vmuluwm (Vector Multiply
+   Unsigned Word Modulo) for both signed and unsigned word multiplication.  */
+
+#define N 128
+
+extern signed int si_a[N], si_b[N], si_c[N];
+extern unsigned int ui_a[N], ui_b[N], ui_c[N];
+
+__attribute__ ((noipa)) void
+test_si ()
+{
+  for (int i = 0; i < N; i++)
+    si_c[i] = si_a[i] * si_b[i];
+}
+
+__attribute__ ((noipa)) void
+test_ui ()
+{
+  for (int i = 0; i < N; i++)
+    ui_c[i] = ui_a[i] * ui_b[i];
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */
+/* { dg-final { scan-assembler-times {\mvmuluwm\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mul-vectorize-2.c b/gcc/testsuite/gcc.target/powerpc/mul-vectorize-2.c
new file mode 100644
index 00000000000..12ca97af409
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/mul-vectorize-2.c
@@ -0,0 +1,27 @@ 
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */
+
+/* Test vectorizer can exploit ISA 3.1 instruction vmulld (Vector Multiply
+   Low Doubleword) for both signed and unsigned doubleword multiplication.  */
+
+#define N 128
+
+extern signed long long sd_a[N], sd_b[N], sd_c[N];
+extern unsigned long long ud_a[N], ud_b[N], ud_c[N];
+
+__attribute__ ((noipa)) void
+test_sd ()
+{
+  for (int i = 0; i < N; i++)
+    sd_c[i] = sd_a[i] * sd_b[i];
+}
+
+__attribute__ ((noipa)) void
+test_ud ()
+{
+  for (int i = 0; i < N; i++)
+    ud_c[i] = ud_a[i] * ud_b[i];
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */
+/* { dg-final { scan-assembler-times {\mvmulld\M} 2 } } */