From patchwork Fri Jul 26 14:05:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1965329 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WVqKP35XRz1yXx for ; Sat, 27 Jul 2024 00:05:43 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D0212386C597 for ; Fri, 26 Jul 2024 14:05:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 9C1863858D26 for ; Fri, 26 Jul 2024 14:05:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9C1863858D26 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9C1863858D26 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722002720; cv=none; b=DI5Ll8FJoCix+ambDUN1fEV12kmwUkanUrryi0x31KLn5M+MyL09zDwa4cGhJCsFAI1aJVziRPrHRwihPz77WIskRyNO+16ou5ZZhahGrPharVJuApCAZuFpsMfymf9IvpqM7ap9Ves/1wDkZxfWl0np+IourCCSwQPg0I58TEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722002720; c=relaxed/simple; bh=qDc9mJ3F+P/JiE3BZsJA+XsmZdV42OuIdnifo1edmRo=; h=Message-ID:Date:MIME-Version:To:From:Subject; b=FC0BmqWGl9IdioYfZ3WnK0WbgSPPMzTytfXyMpdaapJBX2EAQra6o7dPQA0JAEM4xbRoxdw8clfguMqLhYBEOuSTWrfHI82jBzNxxOb7mtRk7+mlqA1kYlgZuYgmex3nbdZSjhJCczKWSam6ks8u+MXwNvH6adFAfSw+mwyTD8Y= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CC2DD1007; Fri, 26 Jul 2024 07:05:43 -0700 (PDT) Received: from [10.57.64.175] (unknown [10.57.64.175]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B8D4A3F5A1; Fri, 26 Jul 2024 07:05:17 -0700 (PDT) Message-ID: Date: Fri, 26 Jul 2024 15:05:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Cc: "Richard Earnshaw (lists)" , Christophe.lyon@arm.com From: "Andre Vieira (lists)" Subject: arm: Prevent ICE when doloop dec_set is not PLUS_EXPR X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch refactors and fixes an issue where arm_mve_dlstp_check_dec_counter was making an assumption about the form of what a candidate for a dec_insn. It also makes sure that if it does not initially encounter a 'set' in such a form it tries to find another set that could be the right one. gcc/ChangeLog: * config/arm/arm.cc (check_dec_insn): New helper function containing code hoisted from... (arm_mve_dlstp_check_dec_counter): ... here. Use check_dec_insn to check the validity of the candidate dec_insn. gcc/testsuite/ChangeLog: * gcc.targer/arm/mve/dlstp-loop-form.c: New test. Regression tested mve.exp for arm-none-eabi with -mcpu=cortex-m85. OK for trunk? Kind regards, Andre Vieira diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 92cd168e65937ef7350477464e8b0becf85bceed..e145a69ed4c6c5b925c1dc2bc25b98f2a1af5849 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -35214,6 +35214,30 @@ arm_mve_dlstp_check_inc_counter (loop *loop, rtx_insn* vctp_insn, return vctp_insn; } +/* Helper function to 'arm_mve_dlstp_check_dec_counter' to make sure DEC_INSN + is of the expected form: + (set (reg a) (plus (reg a) (const_int))) + where (reg a) is the same as CONDCOUNT. */ + +static bool +check_dec_insn (rtx_insn *dec_insn, rtx condcount) +{ + if (!NONDEBUG_INSN_P (dec_insn)) + return false; + rtx dec_set = single_set (dec_insn); + if (!dec_set + || !REG_P (SET_DEST (dec_set)) + || GET_CODE (SET_SRC (dec_set)) != PLUS + || !REG_P (XEXP (SET_SRC (dec_set), 0)) + || !CONST_INT_P (XEXP (SET_SRC (dec_set), 1)) + || REGNO (SET_DEST (dec_set)) + != REGNO (XEXP (SET_SRC (dec_set), 0)) + || REGNO (SET_DEST (dec_set)) != REGNO (condcount)) + return false; + + return true; +} + /* Helper function to `arm_mve_loop_valid_for_dlstp`. In the case of a counter that is decrementing, ensure that it is decrementing by the right amount in each iteration and that the target condition is what @@ -35232,30 +35256,19 @@ arm_mve_dlstp_check_dec_counter (loop *loop, rtx_insn* vctp_insn, modified. */ rtx_insn *dec_insn = BB_END (loop->latch); /* If not in the loop latch, try to find the decrement in the loop header. */ - if (!NONDEBUG_INSN_P (dec_insn)) + if (!check_dec_insn(dec_insn, condcount)) { df_ref temp = df_bb_regno_only_def_find (loop->header, REGNO (condcount)); /* If we haven't been able to find the decrement, bail out. */ if (!temp) return NULL; dec_insn = DF_REF_INSN (temp); - } - rtx dec_set = single_set (dec_insn); - - /* Next, ensure that it is a PLUS of the form: - (set (reg a) (plus (reg a) (const_int))) - where (reg a) is the same as condcount. */ - if (!dec_set - || !REG_P (SET_DEST (dec_set)) - || !REG_P (XEXP (SET_SRC (dec_set), 0)) - || !CONST_INT_P (XEXP (SET_SRC (dec_set), 1)) - || REGNO (SET_DEST (dec_set)) - != REGNO (XEXP (SET_SRC (dec_set), 0)) - || REGNO (SET_DEST (dec_set)) != REGNO (condcount)) - return NULL; + if (!check_dec_insn(dec_insn, condcount)) + return NULL; + } - decrementnum = INTVAL (XEXP (SET_SRC (dec_set), 1)); + decrementnum = INTVAL (XEXP (SET_SRC (single_set (dec_insn)), 1)); /* This decrementnum is the number of lanes/elements it decrements from the remaining number of lanes/elements to process in the loop, for this reason diff --git a/gcc/testsuite/gcc.target/arm/mve/dlstp-loop-form.c b/gcc/testsuite/gcc.target/arm/mve/dlstp-loop-form.c new file mode 100644 index 0000000000000000000000000000000000000000..20c9dcd2984ba75701d853bcbba10caf12b5f2bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/dlstp-loop-form.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-options "-Ofast" } */ +/* { dg-add-options arm_v8_1m_mve } */ +#pragma GCC arm "arm_mve_types.h" +#pragma GCC arm "arm_mve.h" false +typedef __attribute__((aligned(2))) float16x8_t e; +mve_pred16_t c(long d) { return __builtin_mve_vctp16qv8bi(d); } +int f(); +void n() { + int g, h, *i, j; + mve_pred16_t k; + e acc; + e l; + e m; + for (;;) { + j = g; + acc[g]; + for (; h < g; h += 8) { + k = c(j); + acc = vfmsq_m(acc, l, m, k); + j -= 8; + } + i[g] = f(acc); + } +} +