From patchwork Fri May 5 09:41:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1777512 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss-cipunited-com.20200927.dkim.feishu.cn header.i=@oss-cipunited-com.20200927.dkim.feishu.cn header.a=rsa-sha256 header.s=s1 header.b=IPTyga0O; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QCQgq03bpz20fg for ; Fri, 5 May 2023 19:41:58 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 37B0E3853824 for ; Fri, 5 May 2023 09:41:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.33]) by sourceware.org (Postfix) with UTF8SMTPS id 507883858D33 for ; Fri, 5 May 2023 09:41:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 507883858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1683279697; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=2ied4S6UtYN3oxHcGO9FJfPr57SOx8yMBz6hZRjPyFk=; b=IPTyga0O9DiOIUCwzkQ1QMpQ28qk2IQkBHQsrkABKw69wtPMOZBuCMyNEGY0ELLZ9C4y71 Gohn19lcXAzHG42za3EVFlAG+vmJwMDzSwheEohVropVHTD/3izfblCrLjtLH1eWDlfsCD 5HssIB69XDqlkOzrdffU9+as/Lm70JTyFmwMFDwyubJ5saFTktbCnS9vTmZ+N8Sjl7oJ48 JvwXodTuW7+aFKik+ARSJ9djjg7pI2hp4rGqNBWC10FX97/eZYntrh48bdf5p9YkYLi8C2 R9VDnLG/2yGc0VxKr9QFEbIKn3/Ko01MDm5oPZ6uqDrofCSgN8fGVwedUj86fw== Mime-Version: 1.0 X-Mailer: git-send-email 2.40.1 References: From: "Jie Mei" Subject: [PATCH 5/8] MIPS: Add LUI instruction for mips16e2 X-Lms-Return-Path: Message-Id: To: Date: Fri, 05 May 2023 17:41:37 +0800 In-Reply-To: X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, HTML_MESSAGE, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds LUI instruction from mips16e2 with corresponding test. gcc/ChangeLog: * gcc/config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction. (mips_const_insns): Same as above. (mips_output_move): Same as above. (mips_output_function_prologue): Same as above. * gcc/config/mips/mips.md: Same as above gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: Add new tests for mips16e2. --- gcc/config/mips/mips.cc | 44 ++++++++++++++++++------ gcc/config/mips/mips.md | 2 +- gcc/testsuite/gcc.target/mips/mips16e2.c | 22 ++++++++++++ 3 files changed, 56 insertions(+), 12 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index d86911d10c2..0792f89cab4 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2295,7 +2295,9 @@ mips_symbol_insns_1 (enum mips_symbol_type type, machine_mode mode) The final address is then $at + %lo(symbol). With 32-bit symbols we just need a preparatory LUI for normal mode and a preparatory LI and SLL for MIPS16. */ - return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2; + return ABI_HAS_64BIT_SYMBOLS + ? 6 + : (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? 3 : 2; case SYMBOL_GP_RELATIVE: /* Treat GP-relative accesses as taking a single instruction on @@ -2867,7 +2869,7 @@ mips_const_insns (rtx x) /* This is simply an LUI for normal mode. It is an extended LI followed by an extended SLL for MIPS16. */ - return TARGET_MIPS16 ? 4 : 1; + return TARGET_MIPS16 ? (ISA_HAS_MIPS16E2 ? 2 : 4) : 1; case CONST_INT: if (TARGET_MIPS16) @@ -2879,7 +2881,10 @@ mips_const_insns (rtx x) : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 : IN_RANGE (-INTVAL (x), 0, 255) ? 2 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 - : 0); + : ISA_HAS_MIPS16E2 + ? (trunc_int_for_mode (INTVAL (x), SImode) == INTVAL (x) + ? 4 : 8) + : 0); return mips_build_integer (codes, INTVAL (x)); @@ -5252,6 +5257,11 @@ mips_output_move (rtx dest, rtx src) if (!TARGET_MIPS16) return "li\t%0,%1\t\t\t# %X1"; + if (ISA_HAS_MIPS16E2 + && LUI_INT (src) + && !SMALL_OPERAND_UNSIGNED (INTVAL (src))) + return "lui\t%0,%%hi(%1)\t\t\t# %X1"; + if (SMALL_OPERAND_UNSIGNED (INTVAL (src))) return "li\t%0,%1"; @@ -5260,7 +5270,7 @@ mips_output_move (rtx dest, rtx src) } if (src_code == HIGH) - return TARGET_MIPS16 ? "#" : "lui\t%0,%h1"; + return (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? "#" : "lui\t%0,%h1"; if (CONST_GP_P (src)) return "move\t%0,%1"; @@ -11983,13 +11993,25 @@ mips_output_function_prologue (FILE *file) { if (TARGET_MIPS16) { - /* This is a fixed-form sequence. The position of the - first two instructions is important because of the - way _gp_disp is defined. */ - output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); - output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); - output_asm_insn ("sll\t$2,16", 0); - output_asm_insn ("addu\t$2,$3", 0); + if (ISA_HAS_MIPS16E2) + { + /* This is a fixed-form sequence. The position of the + first two instructions is important because of the + way _gp_disp is defined. */ + output_asm_insn ("lui\t$2,%%hi(_gp_disp)", 0); + output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); + output_asm_insn ("addu\t$2,$3", 0); + } + else + { + /* This is a fixed-form sequence. The position of the + first two instructions is important because of the + way _gp_disp is defined. */ + output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); + output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); + output_asm_insn ("sll\t$2,16", 0); + output_asm_insn ("addu\t$2,$3", 0); + } } else { diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 9f652310aa2..73c9acd484f 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4634,7 +4634,7 @@ (define_split [(set (match_operand:P 0 "d_operand") (high:P (match_operand:P 1 "symbolic_operand_with_high")))] - "TARGET_MIPS16 && reload_completed" + "TARGET_MIPS16 && reload_completed && !ISA_HAS_MIPS16E2" [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH)) (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))]) diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c index ce8b4f1819b..780891b4056 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2.c @@ -100,3 +100,25 @@ test08 (unsigned int a) return ((a + 0x2) ^ 0x3f0); } +/* Test LUI. */ + +/* { dg-final { scan-assembler "test09:.*\tlui\t.*test09\n" } } */ +int +test09 (void) +{ + return 0x44440000; +} + +/* Test LUI relocation sequence chang. */ + +/* { dg-final { scan-assembler "test10:.*\tlui\t.*test10\n" } } */ +int *a10; + +int +test10 (int i) +{ + a10 = &i; + *a10 = 0x44440000; + return i; +} +