From patchwork Mon Oct 3 16:45:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 677763 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3snnwx4DFHz9s3v for ; Tue, 4 Oct 2016 03:45:53 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=cou6C1eB; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=Ll/TPyyrAgo4YUyjT CHa0Ltl/UtEFmvJ39qCVAMX5xtn0lveiTEuY0OSv38HnWuT+TO+eNSRw7W2zKU0I L91EA5QBm1KqYML+McbiYShue0jFQwCLys7bcj5Fq6XRFqXZPwBi4UJXEzXcPjM2 iOU1QX0xZJXga1SU6I34rBItb8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=G7cUF/h12fZObcWOK+9p0Rl QnPk=; b=cou6C1eBSTs6Gt1l4wODQIeSQY3Cfpaeujpve559fEDnwKTuhN5hiwk 1gAk3Z+kllAFFteKVJTsp0JsaNCjV2Vks9Fo92dBwghBnjCS+6TxOnh0oMb3tiEt 8JctyqFAPcMctv4KsiI4wYHOcNlmDE7gdBT1EF7Txokd5OlaJcLw= Received: (qmail 37318 invoked by alias); 3 Oct 2016 16:45:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 37188 invoked by uid 89); 3 Oct 2016 16:45:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.5 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=2448 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Oct 2016 16:45:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BBC6546; Mon, 3 Oct 2016 09:45:14 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 08DCB3F218; Mon, 3 Oct 2016 09:45:13 -0700 (PDT) Subject: Re: [PATCH, ARM 4/7, ping] Adapt atomic compare and swap to ARMv8-M Baseline To: "gcc-patches@gcc.gnu.org" , Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw References: From: Thomas Preudhomme Message-ID: Date: Mon, 3 Oct 2016 17:45:12 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes Ping? Best regards, Thomas On 22/09/16 14:46, Thomas Preudhomme wrote: > Hi, > > This patch is part of a patch series to add support for atomic operations on > ARMv8-M Baseline targets in GCC. This specific patch makes the necessary change > for compare and swap to work for ARMv8-M Baseline, doubleword integers excepted. > Namely, it adds Thumb-1 specific constraints to compare_and_swap. The > constraints are chosen so that once the pattern is splitted, the individual > instructions have their constraints respected. In particular, the constraints > for the cbranchsi4_* pattern must be duplicated here, which explains the use of > several alternatives. > > Note: changes to enable other atomic operation are in the next patch of the series. > > ChangeLog entry is as follows: > > *** gcc/ChangeLog *** > > 2016-07-05 Thomas Preud'homme > > * config/arm/sync.md (atomic_compare_and_swap_1): Add new ARMv8-M > Baseline only alternatives to (i) hold store atomic success value in a > return register rather than a scratch register, (ii) use a low register > for it and to (iii) ensure the cbranchsi insn generated by the split > respect the constraints of Thumb-1 cbranchsi4_insn and > cbranchsi4_scratch. > * config/arm/thumb1.md (cbranchsi4_insn): Add comment to indicate > constraints must match those in atomic_compare_and_swap. > (cbranchsi4_scratch): Likewise. > > > Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all > atomic and synchronization testcases in the testsuite [2]. Patchset was also > bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb mode at > optimization level -O1 and above [1] without any regression in the testsuite and > no code generation difference in libitm and libgomp. > > Code generation for ARMv8-M Baseline has been manually examined and compared > against ARMv8-A Thumb-2 for the following configuration without finding any issue: > > gcc.dg/atomic-op-2.c at -Os > gcc.dg/atomic-compare-exchange-2.c at -Os > gcc.dg/atomic-compare-exchange-3.c at -O3 > > > Is this ok for trunk? > > Best regards, > > Thomas > > [1] CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET were set to "-O1 -g", "-O3 -g" and > undefined ("-O2 -g") > [2] The exact list is: > > gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c > gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c > gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c > gcc/testsuite/gcc.dg/atomic-exchange-1.c > gcc/testsuite/gcc.dg/atomic-exchange-2.c > gcc/testsuite/gcc.dg/atomic-exchange-3.c > gcc/testsuite/gcc.dg/atomic-fence.c > gcc/testsuite/gcc.dg/atomic-flag.c > gcc/testsuite/gcc.dg/atomic-generic.c > gcc/testsuite/gcc.dg/atomic-generic-aux.c > gcc/testsuite/gcc.dg/atomic-invalid-2.c > gcc/testsuite/gcc.dg/atomic-load-1.c > gcc/testsuite/gcc.dg/atomic-load-2.c > gcc/testsuite/gcc.dg/atomic-load-3.c > gcc/testsuite/gcc.dg/atomic-lockfree.c > gcc/testsuite/gcc.dg/atomic-lockfree-aux.c > gcc/testsuite/gcc.dg/atomic-noinline.c > gcc/testsuite/gcc.dg/atomic-noinline-aux.c > gcc/testsuite/gcc.dg/atomic-op-1.c > gcc/testsuite/gcc.dg/atomic-op-2.c > gcc/testsuite/gcc.dg/atomic-op-3.c > gcc/testsuite/gcc.dg/atomic-op-6.c > gcc/testsuite/gcc.dg/atomic-store-1.c > gcc/testsuite/gcc.dg/atomic-store-2.c > gcc/testsuite/gcc.dg/atomic-store-3.c > gcc/testsuite/g++.dg/ext/atomic-1.C > gcc/testsuite/g++.dg/ext/atomic-2.C > gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c > gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c > gcc/testsuite/gcc.target/arm/atomic-op-acquire.c > gcc/testsuite/gcc.target/arm/atomic-op-char.c > gcc/testsuite/gcc.target/arm/atomic-op-consume.c > gcc/testsuite/gcc.target/arm/atomic-op-int.c > gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c > gcc/testsuite/gcc.target/arm/atomic-op-release.c > gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c > gcc/testsuite/gcc.target/arm/atomic-op-short.c > gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c > gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c > gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c > gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c > gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c > gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c > gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c > gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c > gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c > gcc/testsuite/gcc.target/arm/sync-1.c > gcc/testsuite/gcc.target/arm/synchronize.c > gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c > gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c > gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c > gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c > libstdc++-v3/testsuite/29_atomics/atomic/60658.cc > libstdc++-v3/testsuite/29_atomics/atomic/62259.cc > libstdc++-v3/testsuite/29_atomics/atomic/64658.cc > libstdc++-v3/testsuite/29_atomics/atomic/65147.cc > libstdc++-v3/testsuite/29_atomics/atomic/65913.cc > libstdc++-v3/testsuite/29_atomics/atomic/70766.cc > libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc > libstdc++-v3/testsuite/29_atomics/atomic/cons/constexpr.cc > libstdc++-v3/testsuite/29_atomics/atomic/cons/copy_list.cc > libstdc++-v3/testsuite/29_atomics/atomic/cons/default.cc > libstdc++-v3/testsuite/29_atomics/atomic/cons/direct_list.cc > libstdc++-v3/testsuite/29_atomics/atomic/cons/single_value.cc > libstdc++-v3/testsuite/29_atomics/atomic/cons/user_pod.cc > libstdc++-v3/testsuite/29_atomics/atomic/operators/51811.cc > libstdc++-v3/testsuite/29_atomics/atomic/operators/56011.cc > libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_assignment.cc > libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_conversion.cc > libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc > libstdc++-v3/testsuite/29_atomics/atomic/requirements/base_classes.cc > libstdc++-v3/testsuite/29_atomics/atomic/requirements/compare_exchange_lowering.cc > libstdc++-v3/testsuite/29_atomics/atomic/requirements/explicit_instantiation/1.cc > libstdc++-v3/testsuite/29_atomics/atomic_flag/clear/1.cc > libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/1.cc > libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/56012.cc > libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/aggregate.cc > libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/default.cc > libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/standard_layout.cc > libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/trivial.cc > libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/explicit.cc > libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/implicit.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/60940.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/65147.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/constexpr.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/copy_list.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/default.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/direct_list.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/single_value.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/bitwise.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/decrement.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/increment.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_assignment.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_conversion.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/standard_layout.cc > libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/trivial.cc > libstdc++-v3/testsuite/29_atomics/headers/atomic/functions_std_c++0x.cc > libstdc++-v3/testsuite/29_atomics/headers/atomic/macros.cc > libstdc++-v3/testsuite/29_atomics/headers/atomic/types_std_c++0x.cc diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index b1e87cdd5d9587d7b301d0dd0072fc41079a04d3..debca40a7ef92e37f0a308d965bd289f6dd74693 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -189,21 +189,23 @@ DONE; }) +;; Constraints of this pattern must be at least as strict as those of the +;; cbranchsi operations in thumb1.md and aim to be as permissive. (define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c") ;; bool out + [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) - (set (match_operand:SI 1 "s_register_operand" "=&r") ;; val out + (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (zero_extend:SI - (match_operand:NARROW 2 "mem_noofs_operand" "+Ua"))) ;; memory + (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))) ;; memory (set (match_dup 2) (unspec_volatile:NARROW - [(match_operand:SI 3 "arm_add_operand" "rIL") ;; expected - (match_operand:NARROW 4 "s_register_operand" "r") ;; desired + [(match_operand:SI 3 "arm_add_operand" "rIL,lIL*h,J,*r") ;; expected + (match_operand:NARROW 4 "s_register_operand" "r,r,r,r") ;; desired (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f VUNSPEC_ATOMIC_CAS)) - (clobber (match_scratch:SI 8 "=&r"))] + (clobber (match_scratch:SI 8 "=&r,X,X,X"))] "" "#" "&& reload_completed" @@ -211,27 +213,30 @@ { arm_split_compare_and_swap (operands); DONE; - }) + } + [(set_attr "arch" "32,v8mb,v8mb,v8mb")]) (define_mode_attr cas_cmp_operand [(SI "arm_add_operand") (DI "cmpdi_operand")]) (define_mode_attr cas_cmp_str [(SI "rIL") (DI "rDi")]) +;; Constraints of this pattern must be at least as strict as those of the +;; cbranchsi operations in thumb1.md and aim to be as permissive. (define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c") ;; bool out + [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) - (set (match_operand:SIDI 1 "s_register_operand" "=&r") ;; val out - (match_operand:SIDI 2 "mem_noofs_operand" "+Ua")) ;; memory + (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out + (match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")) ;; memory (set (match_dup 2) (unspec_volatile:SIDI - [(match_operand:SIDI 3 "" "") ;; expect - (match_operand:SIDI 4 "s_register_operand" "r") ;; desired + [(match_operand:SIDI 3 "" ",lIL*h,J,*r") ;; expect + (match_operand:SIDI 4 "s_register_operand" "r,r,r,r") ;; desired (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f VUNSPEC_ATOMIC_CAS)) - (clobber (match_scratch:SI 8 "=&r"))] + (clobber (match_scratch:SI 8 "=&r,X,X,X"))] "" "#" "&& reload_completed" @@ -239,7 +244,8 @@ { arm_split_compare_and_swap (operands); DONE; - }) + } + [(set_attr "arch" "32,v8mb,v8mb,v8mb")]) (define_insn_and_split "atomic_exchange" [(set (match_operand:QHSD 0 "s_register_operand" "=&r") ;; output diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index cd98de7dcb40de483a9f93c0674bd216f4b0c56a..67f2878b45fe47abaaf24d97213613d1572dcd91 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -1059,6 +1059,9 @@ (const_string "multiple")))] ) +;; Changes to the constraints of this pattern must be propagated to those of +;; atomic compare_and_swap splitters in sync.md. These must be at least as +;; strict as the constraints here and aim to be as permissive. (define_insn "cbranchsi4_insn" [(set (pc) (if_then_else (match_operator 0 "arm_comparison_operator" @@ -1120,6 +1123,9 @@ (set_attr "type" "multiple")] ) +;; Changes to the constraints of this pattern must be propagated to those of +;; atomic compare_and_swap splitters in sync.md. These must be at least as +;; strict as the constraints here and aim to be as permissive. (define_insn "cbranchsi4_scratch" [(set (pc) (if_then_else (match_operator 4 "arm_comparison_operator"