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Wed, 24 Jul 2024 11:00:27 -0700 (PDT) Received: from marvin.dc1.ventanamicro.com ([189.4.72.88]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fd6f4713f8sm97261705ad.268.2024.07.24.11.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jul 2024 11:00:26 -0700 (PDT) From: Raphael Moreira Zinsly To: gcc-patches@gcc.gnu.org Cc: jlaw@ventanamicro.com, Raphael Moreira Zinsly Subject: [PATCH 2/5] RISC-V: Move riscv_v_adjust_scalable_frame Date: Wed, 24 Jul 2024 15:00:10 -0300 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Move riscv_v_adjust_scalable_frame () in preparation for the stack clash protection support. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_v_adjust_scalable_frame): Move closer to riscv_expand_prologue. --- gcc/config/riscv/riscv.cc | 62 +++++++++++++++++++-------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index f85d018c514..89fc8966654 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3122,37 +3122,6 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src) } } -/* Adjust scalable frame of vector for prologue && epilogue. */ - -static void -riscv_v_adjust_scalable_frame (rtx target, poly_int64 offset, bool epilogue) -{ - rtx tmp = RISCV_PROLOGUE_TEMP (Pmode); - rtx adjust_size = RISCV_PROLOGUE_TEMP2 (Pmode); - rtx insn, dwarf, adjust_frame_rtx; - - riscv_legitimize_poly_move (Pmode, adjust_size, tmp, - gen_int_mode (offset, Pmode)); - - if (epilogue) - insn = gen_add3_insn (target, target, adjust_size); - else - insn = gen_sub3_insn (target, target, adjust_size); - - insn = emit_insn (insn); - - RTX_FRAME_RELATED_P (insn) = 1; - - adjust_frame_rtx - = gen_rtx_SET (target, - plus_constant (Pmode, target, epilogue ? offset : -offset)); - - dwarf = alloc_reg_note (REG_FRAME_RELATED_EXPR, copy_rtx (adjust_frame_rtx), - NULL_RTX); - - REG_NOTES (insn) = dwarf; -} - /* Take care below subreg const_poly_int move: 1. (set (subreg:DI (reg:TI 237) 8) @@ -7928,6 +7897,37 @@ static const code_for_push_pop_t code_for_push_pop[ZCMP_MAX_GRP_SLOTS][ZCMP_OP_N code_for_gpr_multi_popret_up_to_s11, code_for_gpr_multi_popretz_up_to_s11}}; +/* Adjust scalable frame of vector for prologue && epilogue. */ + +static void +riscv_v_adjust_scalable_frame (rtx target, poly_int64 offset, bool epilogue) +{ + rtx tmp = RISCV_PROLOGUE_TEMP (Pmode); + rtx adjust_size = RISCV_PROLOGUE_TEMP2 (Pmode); + rtx insn, dwarf, adjust_frame_rtx; + + riscv_legitimize_poly_move (Pmode, adjust_size, tmp, + gen_int_mode (offset, Pmode)); + + if (epilogue) + insn = gen_add3_insn (target, target, adjust_size); + else + insn = gen_sub3_insn (target, target, adjust_size); + + insn = emit_insn (insn); + + RTX_FRAME_RELATED_P (insn) = 1; + + adjust_frame_rtx + = gen_rtx_SET (target, + plus_constant (Pmode, target, epilogue ? offset : -offset)); + + dwarf = alloc_reg_note (REG_FRAME_RELATED_EXPR, copy_rtx (adjust_frame_rtx), + NULL_RTX); + + REG_NOTES (insn) = dwarf; +} + static rtx riscv_gen_multi_push_pop_insn (riscv_zcmp_op_t op, HOST_WIDE_INT adj_size, unsigned int regs_num)