Message ID | cc66a32d-803f-d1f4-b29e-b98e742c02d9@foss.arm.com |
---|---|
State | New |
Headers | show |
On 14/07/17 09:33, Thomas Preudhomme wrote: > Hi, > > On 29/06/17 16:13, Thomas Preudhomme wrote: >> Please ignore this patch. I'll respin the patch on a more recent GCC. > > Please find an updated patch in attachment. > > This patch adds support for the ARM Cortex-R52 processor rencently > announced. > > [1] https://developer.arm.com/products/processors/cortex-r/cortex-r52 > > ChangeLog entry is as follows: > > *** gcc/ChangeLog *** > > 2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> > > * config/arm/arm-cpus.in (cortex-r52): Add new entry. > (armv8-r): Set ARM Cortex-R52 as default CPU. > * config/arm/arm-tables.opt: Regenerate. > * config/arm/arm-tune.md: Regenerate. > * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM > Cortex-R52. > * doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp > extension for -mcpu=cortex-r52. > > Tested by building an arm-none-eabi GCC cross-compiler targeting Cortex-R52 and building an hello world with it. Also checked that the .fpu option created by GCC for -mcpu=cortex-r52 and -mcpu=cortex-r52+nofp.dp is as expected > (respectively .fpu neon-fp-armv8 and .fpu fpv5-sp-d16 > > Is this ok for trunk? > Ok. Thanks, Kyrill > Best regards, > > Thomas
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index e2ff297aed7514073dbb3bf5ee86964f202e5a14..d009a9e18acb093aefe0f9d8d6de49489fc2325c 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -381,7 +381,7 @@ begin arch armv8-m.main end arch armv8-m.main begin arch armv8-r - tune for cortex-r4 + tune for cortex-r52 tune flags CO_PROC base 8R profile R @@ -1315,6 +1315,16 @@ begin cpu cortex-m33 costs v7m end cpu cortex-m33 +# V8 R-profile implementations. +begin cpu cortex-r52 + cname cortexr52 + tune flags LDSCHED + architecture armv8-r+crc+simd + fpu neon-fp-armv8 + option nofp.dp remove FP_DBL ALL_SIMD + costs cortex +end cpu cortex-r52 + # FPU entries # format: # begin fpu <name> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 51678c2566e841894c5c0e9c613c8c0f832e9988..4e508b1555a77628ff6e7cfea39c98b87caa840a 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -357,6 +357,9 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23) EnumValue Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33) +EnumValue +Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) + Enum Name(arm_arch) Type(int) Known ARM architectures (for use with the -march= option): diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index ba2c7d8ecfdbf6966ebf04b680d587a0e057b161..1b3f7a94cc78fac8abf1042ef60c81a74eaf24eb 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -57,5 +57,6 @@ cortexa73,exynosm1,xgene1, cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, cortexa73cortexa53,cortexa55,cortexa75, - cortexa75cortexa55,cortexm23,cortexm33" + cortexa75cortexa55,cortexm23,cortexm33, + cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index 16171d4e801af46ad549314d1f376e90d5bff57c..5c29b94caaba4ff6f89a191f1d8edcf10431c0b3 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -58,6 +58,7 @@ static struct vendor_cpu arm_cpu_table[] = { {"0xc15", "armv7-r", "cortex-r5"}, {"0xc17", "armv7-r", "cortex-r7"}, {"0xc18", "armv7-r", "cortex-r8"}, + {"0xd13", "armv8-r+crc", "cortex-r52"}, {"0xc20", "armv6-m", "cortex-m0"}, {"0xc21", "armv6-m", "cortex-m1"}, {"0xc23", "armv7-m", "cortex-m3"}, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e60edcae53ef3c995054b9b0229b5f0fccbb8462..a093b9bcf77b1f4b40992516e853826bb7d528d4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15538,7 +15538,7 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, -@samp{cortex-r8}, +@samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-m33}, @samp{cortex-m23}, @samp{cortex-m7}, @@ -15628,7 +15628,7 @@ Disables the floating-point and SIMD instructions on @item +nofp.dp Disables the double-precision component of the floating-point instructions -on @samp{cortex-r5} and @samp{cortex-m7}. +on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}. @item +nosimd Disables the SIMD (but not floating-point) instructions on
Hi, On 29/06/17 16:13, Thomas Preudhomme wrote: > Please ignore this patch. I'll respin the patch on a more recent GCC. Please find an updated patch in attachment. This patch adds support for the ARM Cortex-R52 processor rencently announced. [1] https://developer.arm.com/products/processors/cortex-r/cortex-r52 ChangeLog entry is as follows: *** gcc/ChangeLog *** 2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm-cpus.in (cortex-r52): Add new entry. (armv8-r): Set ARM Cortex-R52 as default CPU. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM Cortex-R52. * doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp extension for -mcpu=cortex-r52. Tested by building an arm-none-eabi GCC cross-compiler targeting Cortex-R52 and building an hello world with it. Also checked that the .fpu option created by GCC for -mcpu=cortex-r52 and -mcpu=cortex-r52+nofp.dp is as expected (respectively .fpu neon-fp-armv8 and .fpu fpv5-sp-d16 Is this ok for trunk? Best regards, Thomas