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Fri, 28 Jan 2022 18:03:13 +0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20SI3CJu10944862 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 28 Jan 2022 18:03:12 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 55362AC065; Fri, 28 Jan 2022 18:03:12 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1934CAC062; Fri, 28 Jan 2022 18:03:11 +0000 (GMT) Received: from [9.65.218.28] (unknown [9.65.218.28]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTPS; Fri, 28 Jan 2022 18:03:10 +0000 (GMT) Message-ID: Date: Fri, 28 Jan 2022 12:03:09 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.4.0 Content-Language: en-US Subject: [PATCH, rs6000] Clean up Power10 fusion options To: GCC Patches X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 7XezLbwE3Q3-s2DpIK9qkquT9t4piFbi X-Proofpoint-ORIG-GUID: tL0jN2G3SVA98WUH0aMx87OKioqX9mdW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-28_05,2022-01-28_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201280107 X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_35_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pat Haugen via Gcc-patches From: Pat Haugen Reply-To: Pat Haugen Cc: Peter Bergner , David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Mark Power10 fusion option undocumented and remove sub-options. Bootstrapped and regression tested on powerpc64le(Power10). Ok for master? -Pat 2022-01-28 Pat Haugen gcc/ * config/rs6000/rs6000.opt (mpower10-fusion): Mark Undocumented. (mpower10-fusion-ld-cmpi, mpower10-fusion-2logical, mpower10-fusion-logical-add, mpower10-fusion-add-logical, mpower10-fusion-2add, mpower10-fusion-2store): Remove. * config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER, OTHER_P9_VECTOR_MASKS): Remove Power10 fusion sub-options. * config/rs6000/rs6000.cc (rs6000_option_override_internal, power10_sched_reorder): Likewise. * config/rs6000/genfusion.pl (gen_ld_cmpi_p10, gen_logical_addsubf, gen_addadd): Likewise * config/rs6000/fusion.md: Regenerate. diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index c2a77182a9e..b4e69e9fefd 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -491,33 +491,9 @@ Target Mask(P8_VECTOR) Var(rs6000_isa_flags) Use vector and scalar instructions added in ISA 2.07. mpower10-fusion -Target Mask(P10_FUSION) Var(rs6000_isa_flags) +Target Undocumented Mask(P10_FUSION) Var(rs6000_isa_flags) Fuse certain integer operations together for better performance on power10. -mpower10-fusion-ld-cmpi -Target Undocumented Mask(P10_FUSION_LD_CMPI) Var(rs6000_isa_flags) -Fuse certain integer operations together for better performance on power10. - -mpower10-fusion-2logical -Target Undocumented Mask(P10_FUSION_2LOGICAL) Var(rs6000_isa_flags) -Fuse pairs of scalar or vector logical operations together for better performance on power10. - -mpower10-fusion-logical-add -Target Undocumented Mask(P10_FUSION_LOGADD) Var(rs6000_isa_flags) -Fuse scalar logical op with add/subf for better performance on power10. - -mpower10-fusion-add-logical -Target Undocumented Mask(P10_FUSION_ADDLOG) Var(rs6000_isa_flags) -Fuse scalar add/subf with logical op for better performance on power10. - -mpower10-fusion-2add -Target Undocumented Mask(P10_FUSION_2ADD) Var(rs6000_isa_flags) -Fuse dependent pairs of add or vaddudm instructions for better performance on power10. - -mpower10-fusion-2store -Target Undocumented Mask(P10_FUSION_2STORE) Var(rs6000_isa_flags) -Fuse certain store operations together for better performance on power10. - mcrypto Target Mask(CRYPTO) Var(rs6000_isa_flags) Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 325b21967c4..963947f6939 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -85,13 +85,7 @@ #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS \ - | OPTION_MASK_P10_FUSION \ - | OPTION_MASK_P10_FUSION_LD_CMPI \ - | OPTION_MASK_P10_FUSION_2LOGICAL \ - | OPTION_MASK_P10_FUSION_LOGADD \ - | OPTION_MASK_P10_FUSION_ADDLOG \ - | OPTION_MASK_P10_FUSION_2ADD \ - | OPTION_MASK_P10_FUSION_2STORE) + | OPTION_MASK_P10_FUSION) /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ @@ -139,12 +133,6 @@ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ | OPTION_MASK_P10_FUSION \ - | OPTION_MASK_P10_FUSION_LD_CMPI \ - | OPTION_MASK_P10_FUSION_2LOGICAL \ - | OPTION_MASK_P10_FUSION_LOGADD \ - | OPTION_MASK_P10_FUSION_ADDLOG \ - | OPTION_MASK_P10_FUSION_2ADD \ - | OPTION_MASK_P10_FUSION_2STORE \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index a5fd36b72d9..548366abada 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4458,30 +4458,6 @@ rs6000_option_override_internal (bool global_init_p) && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION; - if (TARGET_POWER10 && - (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LD_CMPI) == 0) - rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LD_CMPI; - - if (TARGET_POWER10 - && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2LOGICAL) == 0) - rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL; - - if (TARGET_POWER10 - && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LOGADD) == 0) - rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LOGADD; - - if (TARGET_POWER10 - && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_ADDLOG) == 0) - rs6000_isa_flags |= OPTION_MASK_P10_FUSION_ADDLOG; - - if (TARGET_POWER10 - && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0) - rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD; - - if (TARGET_POWER10 - && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2STORE) == 0) - rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2STORE; - /* Turn off vector pair/mma options on non-power10 systems. */ else if (!TARGET_POWER10 && TARGET_MMA) { @@ -19110,7 +19086,7 @@ power10_sched_reorder (rtx_insn **ready, int lastpos) /* Try to pair certain store insns to adjacent memory locations so that the hardware will fuse them to a single operation. */ - if (TARGET_P10_FUSION && TARGET_P10_FUSION_2STORE + if (TARGET_P10_FUSION && is_fusable_store (last_scheduled_insn, &mem1)) { diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 7e201f7a3e0..81cc2255f53 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -118,7 +118,7 @@ sub gen_ld_cmpi_p10 } else { print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n"; } - print " \"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)\"\n"; + print " \"(TARGET_P10_FUSION)\"\n"; print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n"; print " \"&& reload_completed\n"; print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n"; @@ -166,8 +166,8 @@ sub gen_logical_addsubf $outer_op, $outer_comp, $outer_inv, $outer_rtl, $inner, @inner_ops, $inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, - $target_flag, $ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42, - $outer_name, $fuse_type); + $ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,$outer_name, + $fuse_type); KIND: foreach $kind ('scalar','vector') { @outer_ops = @logicals; if ( $kind eq 'vector' ) { @@ -199,18 +199,15 @@ sub gen_logical_addsubf $outer_rtl = $rtlop{$outer}; @inner_ops = @logicals; $ftype = "logical-logical"; - $target_flag = "TARGET_P10_FUSION_2LOGICAL"; if ( exists $isaddsub{$outer} ) { @inner_ops = sort keys %logicals_addsub; $ftype = "logical-add"; - $target_flag = "TARGET_P10_FUSION_LOGADD"; } elsif ( $kind ne 'vector' && exists $logicals_addsub{$outer} ) { push (@inner_ops, @addsub); } INNER: foreach $inner ( @inner_ops ) { if ( exists $isaddsub{$inner} ) { $ftype = "add-logical"; - $target_flag = "TARGET_P10_FUSION_ADDLOG"; } $inner_comp = $complement{$inner}; $inner_inv = $invert{$inner}; @@ -266,7 +263,7 @@ sub gen_logical_addsubf [(set (match_operand:${mode} 3 "${pred}" "=&0,&1,&${constraint},${constraint}") ${outer_exp}) (clobber (match_scratch:${mode} 4 "=X,X,X,&${constraint}"))] - "(TARGET_P10_FUSION && $target_flag)" + "(TARGET_P10_FUSION)" "@ ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} @@ -313,7 +310,7 @@ sub gen_addadd (match_operand:${mode} 1 "${pred}" "%${c4}")) (match_operand:${mode} 2 "${pred}" "${c4}"))) (clobber (match_scratch:${mode} 4 "=X,X,X,&${constraint}"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2ADD)" + "(TARGET_P10_FUSION)" "@ ${op} %3,%1,%0\\;${op} %3,%3,%2 ${op} %3,%1,%0\\;${op} %3,%3,%2 diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 6f9f534a0ef..15f0c16f705 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -25,7 +25,7 @@ (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none" (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m") (match_operand:DI 3 "const_m1_to_1_operand" "n"))) (clobber (match_scratch:DI 0 "=r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "ld%X1 %0,%1\;cmpdi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -46,7 +46,7 @@ (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none" (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m") (match_operand:DI 3 "const_0_to_1_operand" "n"))) (clobber (match_scratch:DI 0 "=r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "ld%X1 %0,%1\;cmpldi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -67,7 +67,7 @@ (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none" (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m") (match_operand:DI 3 "const_m1_to_1_operand" "n"))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "ld%X1 %0,%1\;cmpdi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -88,7 +88,7 @@ (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none" (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m") (match_operand:DI 3 "const_0_to_1_operand" "n"))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "ld%X1 %0,%1\;cmpldi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -109,7 +109,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none" (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") (match_operand:SI 3 "const_m1_to_1_operand" "n"))) (clobber (match_scratch:SI 0 "=r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lwa%X1 %0,%1\;cmpdi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -130,7 +130,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_clobber_CCUNS_none" (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") (match_operand:SI 3 "const_0_to_1_operand" "n"))) (clobber (match_scratch:SI 0 "=r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lwz%X1 %0,%1\;cmpldi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -151,7 +151,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none" (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") (match_operand:SI 3 "const_m1_to_1_operand" "n"))) (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lwa%X1 %0,%1\;cmpdi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -172,7 +172,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_SI_CCUNS_none" (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") (match_operand:SI 3 "const_0_to_1_operand" "n"))) (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lwz%X1 %0,%1\;cmpldi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -193,7 +193,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign" (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") (match_operand:SI 3 "const_m1_to_1_operand" "n"))) (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lwa%X1 %0,%1\;cmpdi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -214,7 +214,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") (match_operand:SI 3 "const_0_to_1_operand" "n"))) (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (zero_extend:EXTSI (match_dup 1)))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lwz%X1 %0,%1\;cmpldi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -235,7 +235,7 @@ (define_insn_and_split "*lha_cmpdi_cr0_HI_clobber_CC_sign" (compare:CC (match_operand:HI 1 "non_update_memory_operand" "m") (match_operand:HI 3 "const_m1_to_1_operand" "n"))) (clobber (match_scratch:GPR 0 "=r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lha%X1 %0,%1\;cmpdi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -256,7 +256,7 @@ (define_insn_and_split "*lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" (compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m") (match_operand:HI 3 "const_0_to_1_operand" "n"))) (clobber (match_scratch:GPR 0 "=r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lhz%X1 %0,%1\;cmpldi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -277,7 +277,7 @@ (define_insn_and_split "*lha_cmpdi_cr0_HI_EXTHI_CC_sign" (compare:CC (match_operand:HI 1 "non_update_memory_operand" "m") (match_operand:HI 3 "const_m1_to_1_operand" "n"))) (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (sign_extend:EXTHI (match_dup 1)))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lha%X1 %0,%1\;cmpdi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -298,7 +298,7 @@ (define_insn_and_split "*lhz_cmpldi_cr0_HI_EXTHI_CCUNS_zero" (compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m") (match_operand:HI 3 "const_0_to_1_operand" "n"))) (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (zero_extend:EXTHI (match_dup 1)))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lhz%X1 %0,%1\;cmpldi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -319,7 +319,7 @@ (define_insn_and_split "*lbz_cmpldi_cr0_QI_clobber_CCUNS_zero" (compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m") (match_operand:QI 3 "const_0_to_1_operand" "n"))) (clobber (match_scratch:GPR 0 "=r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lbz%X1 %0,%1\;cmpldi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -340,7 +340,7 @@ (define_insn_and_split "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero" (compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m") (match_operand:QI 3 "const_0_to_1_operand" "n"))) (set (match_operand:GPR 0 "gpc_reg_operand" "=r") (zero_extend:GPR (match_dup 1)))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "(TARGET_P10_FUSION)" "lbz%X1 %0,%1\;cmpldi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) @@ -363,7 +363,7 @@ (define_insn "*fuse_and_and" (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;and %3,%3,%2 and %3,%1,%0\;and %3,%3,%2 @@ -381,7 +381,7 @@ (define_insn "*fuse_andc_and" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ andc %3,%1,%0\;and %3,%3,%2 andc %3,%1,%0\;and %3,%3,%2 @@ -399,7 +399,7 @@ (define_insn "*fuse_eqv_and" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ eqv %3,%1,%0\;and %3,%3,%2 eqv %3,%1,%0\;and %3,%3,%2 @@ -417,7 +417,7 @@ (define_insn "*fuse_nand_and" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;and %3,%3,%2 nand %3,%1,%0\;and %3,%3,%2 @@ -435,7 +435,7 @@ (define_insn "*fuse_nor_and" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;and %3,%3,%2 nor %3,%1,%0\;and %3,%3,%2 @@ -453,7 +453,7 @@ (define_insn "*fuse_or_and" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;and %3,%3,%2 or %3,%1,%0\;and %3,%3,%2 @@ -471,7 +471,7 @@ (define_insn "*fuse_orc_and" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ orc %3,%1,%0\;and %3,%3,%2 orc %3,%1,%0\;and %3,%3,%2 @@ -489,7 +489,7 @@ (define_insn "*fuse_xor_and" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ xor %3,%1,%0\;and %3,%3,%2 xor %3,%1,%0\;and %3,%3,%2 @@ -507,7 +507,7 @@ (define_insn "*fuse_add_and" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "(TARGET_P10_FUSION)" "@ add %3,%1,%0\;and %3,%3,%2 add %3,%1,%0\;and %3,%3,%2 @@ -525,7 +525,7 @@ (define_insn "*fuse_subf_and" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "(TARGET_P10_FUSION)" "@ subf %3,%1,%0\;and %3,%3,%2 subf %3,%1,%0\;and %3,%3,%2 @@ -543,7 +543,7 @@ (define_insn "*fuse_and_andc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;andc %3,%3,%2 and %3,%1,%0\;andc %3,%3,%2 @@ -561,7 +561,7 @@ (define_insn "*fuse_andc_andc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ andc %3,%1,%0\;andc %3,%3,%2 andc %3,%1,%0\;andc %3,%3,%2 @@ -579,7 +579,7 @@ (define_insn "*fuse_eqv_andc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ eqv %3,%1,%0\;andc %3,%3,%2 eqv %3,%1,%0\;andc %3,%3,%2 @@ -597,7 +597,7 @@ (define_insn "*fuse_nand_andc" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;andc %3,%3,%2 nand %3,%1,%0\;andc %3,%3,%2 @@ -615,7 +615,7 @@ (define_insn "*fuse_nor_andc" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;andc %3,%3,%2 nor %3,%1,%0\;andc %3,%3,%2 @@ -633,7 +633,7 @@ (define_insn "*fuse_or_andc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;andc %3,%3,%2 or %3,%1,%0\;andc %3,%3,%2 @@ -651,7 +651,7 @@ (define_insn "*fuse_orc_andc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ orc %3,%1,%0\;andc %3,%3,%2 orc %3,%1,%0\;andc %3,%3,%2 @@ -669,7 +669,7 @@ (define_insn "*fuse_xor_andc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ xor %3,%1,%0\;andc %3,%3,%2 xor %3,%1,%0\;andc %3,%3,%2 @@ -687,7 +687,7 @@ (define_insn "*fuse_and_eqv" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;eqv %3,%3,%2 and %3,%1,%0\;eqv %3,%3,%2 @@ -705,7 +705,7 @@ (define_insn "*fuse_andc_eqv" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ andc %3,%1,%0\;eqv %3,%3,%2 andc %3,%1,%0\;eqv %3,%3,%2 @@ -723,7 +723,7 @@ (define_insn "*fuse_eqv_eqv" (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ eqv %3,%1,%0\;eqv %3,%3,%2 eqv %3,%1,%0\;eqv %3,%3,%2 @@ -741,7 +741,7 @@ (define_insn "*fuse_nand_eqv" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;eqv %3,%3,%2 nand %3,%1,%0\;eqv %3,%3,%2 @@ -759,7 +759,7 @@ (define_insn "*fuse_nor_eqv" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;eqv %3,%3,%2 nor %3,%1,%0\;eqv %3,%3,%2 @@ -777,7 +777,7 @@ (define_insn "*fuse_or_eqv" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;eqv %3,%3,%2 or %3,%1,%0\;eqv %3,%3,%2 @@ -795,7 +795,7 @@ (define_insn "*fuse_orc_eqv" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ orc %3,%1,%0\;eqv %3,%3,%2 orc %3,%1,%0\;eqv %3,%3,%2 @@ -813,7 +813,7 @@ (define_insn "*fuse_xor_eqv" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ xor %3,%1,%0\;eqv %3,%3,%2 xor %3,%1,%0\;eqv %3,%3,%2 @@ -831,7 +831,7 @@ (define_insn "*fuse_and_nand" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;nand %3,%3,%2 and %3,%1,%0\;nand %3,%3,%2 @@ -849,7 +849,7 @@ (define_insn "*fuse_andc_nand" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ andc %3,%1,%0\;nand %3,%3,%2 andc %3,%1,%0\;nand %3,%3,%2 @@ -867,7 +867,7 @@ (define_insn "*fuse_eqv_nand" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ eqv %3,%1,%0\;nand %3,%3,%2 eqv %3,%1,%0\;nand %3,%3,%2 @@ -885,7 +885,7 @@ (define_insn "*fuse_nand_nand" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;nand %3,%3,%2 nand %3,%1,%0\;nand %3,%3,%2 @@ -903,7 +903,7 @@ (define_insn "*fuse_nor_nand" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;nand %3,%3,%2 nor %3,%1,%0\;nand %3,%3,%2 @@ -921,7 +921,7 @@ (define_insn "*fuse_or_nand" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;nand %3,%3,%2 or %3,%1,%0\;nand %3,%3,%2 @@ -939,7 +939,7 @@ (define_insn "*fuse_orc_nand" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ orc %3,%1,%0\;nand %3,%3,%2 orc %3,%1,%0\;nand %3,%3,%2 @@ -957,7 +957,7 @@ (define_insn "*fuse_xor_nand" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ xor %3,%1,%0\;nand %3,%3,%2 xor %3,%1,%0\;nand %3,%3,%2 @@ -975,7 +975,7 @@ (define_insn "*fuse_add_nand" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "(TARGET_P10_FUSION)" "@ add %3,%1,%0\;nand %3,%3,%2 add %3,%1,%0\;nand %3,%3,%2 @@ -993,7 +993,7 @@ (define_insn "*fuse_subf_nand" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "(TARGET_P10_FUSION)" "@ subf %3,%1,%0\;nand %3,%3,%2 subf %3,%1,%0\;nand %3,%3,%2 @@ -1011,7 +1011,7 @@ (define_insn "*fuse_and_nor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;nor %3,%3,%2 and %3,%1,%0\;nor %3,%3,%2 @@ -1029,7 +1029,7 @@ (define_insn "*fuse_andc_nor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ andc %3,%1,%0\;nor %3,%3,%2 andc %3,%1,%0\;nor %3,%3,%2 @@ -1047,7 +1047,7 @@ (define_insn "*fuse_eqv_nor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ eqv %3,%1,%0\;nor %3,%3,%2 eqv %3,%1,%0\;nor %3,%3,%2 @@ -1065,7 +1065,7 @@ (define_insn "*fuse_nand_nor" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;nor %3,%3,%2 nand %3,%1,%0\;nor %3,%3,%2 @@ -1083,7 +1083,7 @@ (define_insn "*fuse_nor_nor" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;nor %3,%3,%2 nor %3,%1,%0\;nor %3,%3,%2 @@ -1101,7 +1101,7 @@ (define_insn "*fuse_or_nor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;nor %3,%3,%2 or %3,%1,%0\;nor %3,%3,%2 @@ -1119,7 +1119,7 @@ (define_insn "*fuse_orc_nor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ orc %3,%1,%0\;nor %3,%3,%2 orc %3,%1,%0\;nor %3,%3,%2 @@ -1137,7 +1137,7 @@ (define_insn "*fuse_xor_nor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ xor %3,%1,%0\;nor %3,%3,%2 xor %3,%1,%0\;nor %3,%3,%2 @@ -1155,7 +1155,7 @@ (define_insn "*fuse_add_nor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "(TARGET_P10_FUSION)" "@ add %3,%1,%0\;nor %3,%3,%2 add %3,%1,%0\;nor %3,%3,%2 @@ -1173,7 +1173,7 @@ (define_insn "*fuse_subf_nor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "(TARGET_P10_FUSION)" "@ subf %3,%1,%0\;nor %3,%3,%2 subf %3,%1,%0\;nor %3,%3,%2 @@ -1191,7 +1191,7 @@ (define_insn "*fuse_and_or" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;or %3,%3,%2 and %3,%1,%0\;or %3,%3,%2 @@ -1209,7 +1209,7 @@ (define_insn "*fuse_andc_or" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ andc %3,%1,%0\;or %3,%3,%2 andc %3,%1,%0\;or %3,%3,%2 @@ -1227,7 +1227,7 @@ (define_insn "*fuse_eqv_or" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ eqv %3,%1,%0\;or %3,%3,%2 eqv %3,%1,%0\;or %3,%3,%2 @@ -1245,7 +1245,7 @@ (define_insn "*fuse_nand_or" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;or %3,%3,%2 nand %3,%1,%0\;or %3,%3,%2 @@ -1263,7 +1263,7 @@ (define_insn "*fuse_nor_or" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;or %3,%3,%2 nor %3,%1,%0\;or %3,%3,%2 @@ -1281,7 +1281,7 @@ (define_insn "*fuse_or_or" (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;or %3,%3,%2 or %3,%1,%0\;or %3,%3,%2 @@ -1299,7 +1299,7 @@ (define_insn "*fuse_orc_or" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ orc %3,%1,%0\;or %3,%3,%2 orc %3,%1,%0\;or %3,%3,%2 @@ -1317,7 +1317,7 @@ (define_insn "*fuse_xor_or" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ xor %3,%1,%0\;or %3,%3,%2 xor %3,%1,%0\;or %3,%3,%2 @@ -1335,7 +1335,7 @@ (define_insn "*fuse_add_or" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "(TARGET_P10_FUSION)" "@ add %3,%1,%0\;or %3,%3,%2 add %3,%1,%0\;or %3,%3,%2 @@ -1353,7 +1353,7 @@ (define_insn "*fuse_subf_or" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "(TARGET_P10_FUSION)" "@ subf %3,%1,%0\;or %3,%3,%2 subf %3,%1,%0\;or %3,%3,%2 @@ -1371,7 +1371,7 @@ (define_insn "*fuse_and_orc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;orc %3,%3,%2 and %3,%1,%0\;orc %3,%3,%2 @@ -1389,7 +1389,7 @@ (define_insn "*fuse_andc_orc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ andc %3,%1,%0\;orc %3,%3,%2 andc %3,%1,%0\;orc %3,%3,%2 @@ -1407,7 +1407,7 @@ (define_insn "*fuse_eqv_orc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ eqv %3,%1,%0\;orc %3,%3,%2 eqv %3,%1,%0\;orc %3,%3,%2 @@ -1425,7 +1425,7 @@ (define_insn "*fuse_nand_orc" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;orc %3,%3,%2 nand %3,%1,%0\;orc %3,%3,%2 @@ -1443,7 +1443,7 @@ (define_insn "*fuse_nor_orc" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;orc %3,%3,%2 nor %3,%1,%0\;orc %3,%3,%2 @@ -1461,7 +1461,7 @@ (define_insn "*fuse_or_orc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;orc %3,%3,%2 or %3,%1,%0\;orc %3,%3,%2 @@ -1479,7 +1479,7 @@ (define_insn "*fuse_orc_orc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ orc %3,%1,%0\;orc %3,%3,%2 orc %3,%1,%0\;orc %3,%3,%2 @@ -1497,7 +1497,7 @@ (define_insn "*fuse_xor_orc" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ xor %3,%1,%0\;orc %3,%3,%2 xor %3,%1,%0\;orc %3,%3,%2 @@ -1515,7 +1515,7 @@ (define_insn "*fuse_and_xor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;xor %3,%3,%2 and %3,%1,%0\;xor %3,%3,%2 @@ -1533,7 +1533,7 @@ (define_insn "*fuse_andc_xor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ andc %3,%1,%0\;xor %3,%3,%2 andc %3,%1,%0\;xor %3,%3,%2 @@ -1551,7 +1551,7 @@ (define_insn "*fuse_eqv_xor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ eqv %3,%1,%0\;xor %3,%3,%2 eqv %3,%1,%0\;xor %3,%3,%2 @@ -1569,7 +1569,7 @@ (define_insn "*fuse_nand_xor" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;xor %3,%3,%2 nand %3,%1,%0\;xor %3,%3,%2 @@ -1587,7 +1587,7 @@ (define_insn "*fuse_nor_xor" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;xor %3,%3,%2 nor %3,%1,%0\;xor %3,%3,%2 @@ -1605,7 +1605,7 @@ (define_insn "*fuse_or_xor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;xor %3,%3,%2 or %3,%1,%0\;xor %3,%3,%2 @@ -1623,7 +1623,7 @@ (define_insn "*fuse_orc_xor" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ orc %3,%1,%0\;xor %3,%3,%2 orc %3,%1,%0\;xor %3,%3,%2 @@ -1641,7 +1641,7 @@ (define_insn "*fuse_xor_xor" (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ xor %3,%1,%0\;xor %3,%3,%2 xor %3,%1,%0\;xor %3,%3,%2 @@ -1659,7 +1659,7 @@ (define_insn "*fuse_and_add" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;add %3,%3,%2 and %3,%1,%0\;add %3,%3,%2 @@ -1677,7 +1677,7 @@ (define_insn "*fuse_nand_add" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;add %3,%3,%2 nand %3,%1,%0\;add %3,%3,%2 @@ -1695,7 +1695,7 @@ (define_insn "*fuse_nor_add" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;add %3,%3,%2 nor %3,%1,%0\;add %3,%3,%2 @@ -1713,7 +1713,7 @@ (define_insn "*fuse_or_add" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;add %3,%3,%2 or %3,%1,%0\;add %3,%3,%2 @@ -1731,7 +1731,7 @@ (define_insn "*fuse_and_subf" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;subf %3,%2,%3 and %3,%1,%0\;subf %3,%2,%3 @@ -1749,7 +1749,7 @@ (define_insn "*fuse_nand_subf" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;subf %3,%2,%3 nand %3,%1,%0\;subf %3,%2,%3 @@ -1767,7 +1767,7 @@ (define_insn "*fuse_nor_subf" (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;subf %3,%2,%3 nor %3,%1,%0\;subf %3,%2,%3 @@ -1785,7 +1785,7 @@ (define_insn "*fuse_or_subf" (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;subf %3,%2,%3 or %3,%1,%0\;subf %3,%2,%3 @@ -1803,7 +1803,7 @@ (define_insn "*fuse_and_rsubf" (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ and %3,%1,%0\;subf %3,%3,%2 and %3,%1,%0\;subf %3,%3,%2 @@ -1821,7 +1821,7 @@ (define_insn "*fuse_nand_rsubf" (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ nand %3,%1,%0\;subf %3,%3,%2 nand %3,%1,%0\;subf %3,%3,%2 @@ -1839,7 +1839,7 @@ (define_insn "*fuse_nor_rsubf" (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ nor %3,%1,%0\;subf %3,%3,%2 nor %3,%1,%0\;subf %3,%3,%2 @@ -1857,7 +1857,7 @@ (define_insn "*fuse_or_rsubf" (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "(TARGET_P10_FUSION)" "@ or %3,%1,%0\;subf %3,%3,%2 or %3,%1,%0\;subf %3,%3,%2 @@ -1875,7 +1875,7 @@ (define_insn "*fuse_vand_vand" (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vand %3,%3,%2 vand %3,%1,%0\;vand %3,%3,%2 @@ -1893,7 +1893,7 @@ (define_insn "*fuse_vandc_vand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vand %3,%3,%2 vandc %3,%1,%0\;vand %3,%3,%2 @@ -1911,7 +1911,7 @@ (define_insn "*fuse_veqv_vand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vand %3,%3,%2 veqv %3,%1,%0\;vand %3,%3,%2 @@ -1929,7 +1929,7 @@ (define_insn "*fuse_vnand_vand" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vand %3,%3,%2 vnand %3,%1,%0\;vand %3,%3,%2 @@ -1947,7 +1947,7 @@ (define_insn "*fuse_vnor_vand" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vand %3,%3,%2 vnor %3,%1,%0\;vand %3,%3,%2 @@ -1965,7 +1965,7 @@ (define_insn "*fuse_vor_vand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vand %3,%3,%2 vor %3,%1,%0\;vand %3,%3,%2 @@ -1983,7 +1983,7 @@ (define_insn "*fuse_vorc_vand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vand %3,%3,%2 vorc %3,%1,%0\;vand %3,%3,%2 @@ -2001,7 +2001,7 @@ (define_insn "*fuse_vxor_vand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vand %3,%3,%2 vxor %3,%1,%0\;vand %3,%3,%2 @@ -2019,7 +2019,7 @@ (define_insn "*fuse_vand_vandc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vandc %3,%3,%2 vand %3,%1,%0\;vandc %3,%3,%2 @@ -2037,7 +2037,7 @@ (define_insn "*fuse_vandc_vandc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vandc %3,%3,%2 vandc %3,%1,%0\;vandc %3,%3,%2 @@ -2055,7 +2055,7 @@ (define_insn "*fuse_veqv_vandc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vandc %3,%3,%2 veqv %3,%1,%0\;vandc %3,%3,%2 @@ -2073,7 +2073,7 @@ (define_insn "*fuse_vnand_vandc" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vandc %3,%3,%2 vnand %3,%1,%0\;vandc %3,%3,%2 @@ -2091,7 +2091,7 @@ (define_insn "*fuse_vnor_vandc" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vandc %3,%3,%2 vnor %3,%1,%0\;vandc %3,%3,%2 @@ -2109,7 +2109,7 @@ (define_insn "*fuse_vor_vandc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vandc %3,%3,%2 vor %3,%1,%0\;vandc %3,%3,%2 @@ -2127,7 +2127,7 @@ (define_insn "*fuse_vorc_vandc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vandc %3,%3,%2 vorc %3,%1,%0\;vandc %3,%3,%2 @@ -2145,7 +2145,7 @@ (define_insn "*fuse_vxor_vandc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vandc %3,%3,%2 vxor %3,%1,%0\;vandc %3,%3,%2 @@ -2163,7 +2163,7 @@ (define_insn "*fuse_vand_veqv" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;veqv %3,%3,%2 vand %3,%1,%0\;veqv %3,%3,%2 @@ -2181,7 +2181,7 @@ (define_insn "*fuse_vandc_veqv" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;veqv %3,%3,%2 vandc %3,%1,%0\;veqv %3,%3,%2 @@ -2199,7 +2199,7 @@ (define_insn "*fuse_veqv_veqv" (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;veqv %3,%3,%2 veqv %3,%1,%0\;veqv %3,%3,%2 @@ -2217,7 +2217,7 @@ (define_insn "*fuse_vnand_veqv" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;veqv %3,%3,%2 vnand %3,%1,%0\;veqv %3,%3,%2 @@ -2235,7 +2235,7 @@ (define_insn "*fuse_vnor_veqv" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;veqv %3,%3,%2 vnor %3,%1,%0\;veqv %3,%3,%2 @@ -2253,7 +2253,7 @@ (define_insn "*fuse_vor_veqv" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;veqv %3,%3,%2 vor %3,%1,%0\;veqv %3,%3,%2 @@ -2271,7 +2271,7 @@ (define_insn "*fuse_vorc_veqv" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;veqv %3,%3,%2 vorc %3,%1,%0\;veqv %3,%3,%2 @@ -2289,7 +2289,7 @@ (define_insn "*fuse_vxor_veqv" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;veqv %3,%3,%2 vxor %3,%1,%0\;veqv %3,%3,%2 @@ -2307,7 +2307,7 @@ (define_insn "*fuse_vand_vnand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vnand %3,%3,%2 vand %3,%1,%0\;vnand %3,%3,%2 @@ -2325,7 +2325,7 @@ (define_insn "*fuse_vandc_vnand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vnand %3,%3,%2 vandc %3,%1,%0\;vnand %3,%3,%2 @@ -2343,7 +2343,7 @@ (define_insn "*fuse_veqv_vnand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vnand %3,%3,%2 veqv %3,%1,%0\;vnand %3,%3,%2 @@ -2361,7 +2361,7 @@ (define_insn "*fuse_vnand_vnand" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vnand %3,%3,%2 vnand %3,%1,%0\;vnand %3,%3,%2 @@ -2379,7 +2379,7 @@ (define_insn "*fuse_vnor_vnand" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vnand %3,%3,%2 vnor %3,%1,%0\;vnand %3,%3,%2 @@ -2397,7 +2397,7 @@ (define_insn "*fuse_vor_vnand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vnand %3,%3,%2 vor %3,%1,%0\;vnand %3,%3,%2 @@ -2415,7 +2415,7 @@ (define_insn "*fuse_vorc_vnand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vnand %3,%3,%2 vorc %3,%1,%0\;vnand %3,%3,%2 @@ -2433,7 +2433,7 @@ (define_insn "*fuse_vxor_vnand" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vnand %3,%3,%2 vxor %3,%1,%0\;vnand %3,%3,%2 @@ -2451,7 +2451,7 @@ (define_insn "*fuse_vand_vnor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vnor %3,%3,%2 vand %3,%1,%0\;vnor %3,%3,%2 @@ -2469,7 +2469,7 @@ (define_insn "*fuse_vandc_vnor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vnor %3,%3,%2 vandc %3,%1,%0\;vnor %3,%3,%2 @@ -2487,7 +2487,7 @@ (define_insn "*fuse_veqv_vnor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vnor %3,%3,%2 veqv %3,%1,%0\;vnor %3,%3,%2 @@ -2505,7 +2505,7 @@ (define_insn "*fuse_vnand_vnor" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vnor %3,%3,%2 vnand %3,%1,%0\;vnor %3,%3,%2 @@ -2523,7 +2523,7 @@ (define_insn "*fuse_vnor_vnor" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vnor %3,%3,%2 vnor %3,%1,%0\;vnor %3,%3,%2 @@ -2541,7 +2541,7 @@ (define_insn "*fuse_vor_vnor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vnor %3,%3,%2 vor %3,%1,%0\;vnor %3,%3,%2 @@ -2559,7 +2559,7 @@ (define_insn "*fuse_vorc_vnor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vnor %3,%3,%2 vorc %3,%1,%0\;vnor %3,%3,%2 @@ -2577,7 +2577,7 @@ (define_insn "*fuse_vxor_vnor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vnor %3,%3,%2 vxor %3,%1,%0\;vnor %3,%3,%2 @@ -2595,7 +2595,7 @@ (define_insn "*fuse_vand_vor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vor %3,%3,%2 vand %3,%1,%0\;vor %3,%3,%2 @@ -2613,7 +2613,7 @@ (define_insn "*fuse_vandc_vor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vor %3,%3,%2 vandc %3,%1,%0\;vor %3,%3,%2 @@ -2631,7 +2631,7 @@ (define_insn "*fuse_veqv_vor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vor %3,%3,%2 veqv %3,%1,%0\;vor %3,%3,%2 @@ -2649,7 +2649,7 @@ (define_insn "*fuse_vnand_vor" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vor %3,%3,%2 vnand %3,%1,%0\;vor %3,%3,%2 @@ -2667,7 +2667,7 @@ (define_insn "*fuse_vnor_vor" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vor %3,%3,%2 vnor %3,%1,%0\;vor %3,%3,%2 @@ -2685,7 +2685,7 @@ (define_insn "*fuse_vor_vor" (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vor %3,%3,%2 vor %3,%1,%0\;vor %3,%3,%2 @@ -2703,7 +2703,7 @@ (define_insn "*fuse_vorc_vor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vor %3,%3,%2 vorc %3,%1,%0\;vor %3,%3,%2 @@ -2721,7 +2721,7 @@ (define_insn "*fuse_vxor_vor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vor %3,%3,%2 vxor %3,%1,%0\;vor %3,%3,%2 @@ -2739,7 +2739,7 @@ (define_insn "*fuse_vand_vorc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vorc %3,%3,%2 vand %3,%1,%0\;vorc %3,%3,%2 @@ -2757,7 +2757,7 @@ (define_insn "*fuse_vandc_vorc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vorc %3,%3,%2 vandc %3,%1,%0\;vorc %3,%3,%2 @@ -2775,7 +2775,7 @@ (define_insn "*fuse_veqv_vorc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vorc %3,%3,%2 veqv %3,%1,%0\;vorc %3,%3,%2 @@ -2793,7 +2793,7 @@ (define_insn "*fuse_vnand_vorc" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vorc %3,%3,%2 vnand %3,%1,%0\;vorc %3,%3,%2 @@ -2811,7 +2811,7 @@ (define_insn "*fuse_vnor_vorc" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vorc %3,%3,%2 vnor %3,%1,%0\;vorc %3,%3,%2 @@ -2829,7 +2829,7 @@ (define_insn "*fuse_vor_vorc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vorc %3,%3,%2 vor %3,%1,%0\;vorc %3,%3,%2 @@ -2847,7 +2847,7 @@ (define_insn "*fuse_vorc_vorc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vorc %3,%3,%2 vorc %3,%1,%0\;vorc %3,%3,%2 @@ -2865,7 +2865,7 @@ (define_insn "*fuse_vxor_vorc" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vorc %3,%3,%2 vxor %3,%1,%0\;vorc %3,%3,%2 @@ -2883,7 +2883,7 @@ (define_insn "*fuse_vand_vxor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vxor %3,%3,%2 vand %3,%1,%0\;vxor %3,%3,%2 @@ -2901,7 +2901,7 @@ (define_insn "*fuse_vandc_vxor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vxor %3,%3,%2 vandc %3,%1,%0\;vxor %3,%3,%2 @@ -2919,7 +2919,7 @@ (define_insn "*fuse_veqv_vxor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vxor %3,%3,%2 veqv %3,%1,%0\;vxor %3,%3,%2 @@ -2937,7 +2937,7 @@ (define_insn "*fuse_vnand_vxor" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vxor %3,%3,%2 vnand %3,%1,%0\;vxor %3,%3,%2 @@ -2955,7 +2955,7 @@ (define_insn "*fuse_vnor_vxor" (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vxor %3,%3,%2 vnor %3,%1,%0\;vxor %3,%3,%2 @@ -2973,7 +2973,7 @@ (define_insn "*fuse_vor_vxor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vxor %3,%3,%2 vor %3,%1,%0\;vxor %3,%3,%2 @@ -2991,7 +2991,7 @@ (define_insn "*fuse_vorc_vxor" (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vxor %3,%3,%2 vorc %3,%1,%0\;vxor %3,%3,%2 @@ -3009,7 +3009,7 @@ (define_insn "*fuse_vxor_vxor" (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vxor %3,%3,%2 vxor %3,%1,%0\;vxor %3,%3,%2 @@ -3027,7 +3027,7 @@ (define_insn "*fuse_add_add" (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2ADD)" + "(TARGET_P10_FUSION)" "@ add %3,%1,%0\;add %3,%3,%2 add %3,%1,%0\;add %3,%3,%2 @@ -3045,7 +3045,7 @@ (define_insn "*fuse_vaddudm_vaddudm" (match_operand:V2DI 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:V2DI 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:V2DI 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2ADD)" + "(TARGET_P10_FUSION)" "@ vaddudm %3,%1,%0\;vaddudm %3,%3,%2 vaddudm %3,%1,%0\;vaddudm %3,%3,%2