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[to-be-committed,RISC-V] Avoid unnecessary extensions when value is already extended

Message ID c0a319d1-3990-4592-8732-1ff1a8847c7a@ventanamicro.com
State New
Headers show
Series [to-be-committed,RISC-V] Avoid unnecessary extensions when value is already extended | expand

Commit Message

Jeff Law Oct. 12, 2024, 3:05 p.m. UTC 
This is a minor patch from Jivan from roughly a year ago.  The basic 
idea here is similar to what we do when extending values for the sake of 
comparisons.  Specifically if the value is already known to be properly 
extended, then an extension is just a copy.

The original idea was to use a similar patch, but which aborted to 
identify cases where these unnecessary promotions where emitted.  All 
that showed up when doing a testsuite run with that abort was the 
promotions created by the arithmetic with overflow patterns such as addv.

Things like addv aren't *that* common so this never got high on my todo 
list, even after a minor issue in this space was raised in bugzilla.

But with stage1 closing soon and no good reason not to go forward, I'm 
submitting this into the pre-commit tester now.  My tester has been 
using it since roughly Feb :-)  Plan would be to commit after the 
pre-commit tester renders its verdict.

Jeff
* config/riscv/riscv.md (zero_extendsidi2): If RHS is already
	zero extended, then this is just a copy.
	(extendsidi2): Similarly, but for sign extension.
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Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 89095afeea5..ec00ce1c463 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1773,7 +1773,15 @@  (define_insn "truncdfhf2"
 (define_expand "zero_extendsidi2"
   [(set (match_operand:DI 0 "register_operand")
 	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
-  "TARGET_64BIT")
+  "TARGET_64BIT"
+{
+  if (SUBREG_P (operands[1]) && SUBREG_PROMOTED_VAR_P (operands[1])
+      && SUBREG_PROMOTED_UNSIGNED_P (operands[1]))
+    {
+      emit_insn (gen_movdi (operands[0], SUBREG_REG (operands[1])));
+      DONE;
+    }
+})
 
 (define_insn_and_split "*zero_extendsidi2_internal"
   [(set (match_operand:DI     0 "register_operand"     "=r,r")
@@ -1854,7 +1862,15 @@  (define_expand "extendsidi2"
   [(set (match_operand:DI     0 "register_operand"     "=r,r")
 	(sign_extend:DI
 	    (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
-  "TARGET_64BIT")
+  "TARGET_64BIT"
+{
+  if (SUBREG_P (operands[1]) && SUBREG_PROMOTED_VAR_P (operands[1])
+      && SUBREG_PROMOTED_SIGNED_P (operands[1]))
+    {
+      emit_insn (gen_movdi (operands[0], SUBREG_REG (operands[1])));
+      DONE;
+    }
+})
 
 (define_insn "*extendsidi2_internal"
   [(set (match_operand:DI     0 "register_operand"     "=r,r")